Linear systolic multiplier/squarer for fast exponentiation

Information Processing Letters

Volumn 76, Issue 3, 2000, Pages 105-111

  Lee, Keon Jik ^a   Yoo, Kee Young ^a  

^a Kyungpook National University   (South Korea)

Author keywords

[No Author keywords available]

Indexed keywords

MULTIPLYING CIRCUITS; SYSTOLIC ARRAYS;

EXPONENTIATION; LINEAR SYSTOLIC MULTIPLIER/SQUARERS;

CRYPTOGRAPHY;

EID: 0034543175     PISSN: 00200190     EISSN: None     Source Type: Journal    
DOI: 10.1016/S0020-0190(00)00131-9     Document Type: Article

References (8)

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3. Heo Y.J., Lee K.J., Yoo K.Y. An optimal linear systolic array for computing montgomery modular multiplication. Proc. 10th IASTED International Conference on Parallel and Distributed Computing and Systems. 1998;581-585.
4. Knuth D.E. The Art of Computer Programming, Vol. 2: Seminumerical Algorithms. 2nd ed. 1981;Addition-Wesley, Reading, MA.
5. Kung S.Y. VLSI Array Processors. 1987;Prentice-Hall, Englewood Cliffs, NJ.
6. Montgomery P.L. Modular multiplication without trial division. Math. Comp. Vol. 44:1985;519-521.
7. Rivest R.L., Shamir A., Adleman L. A method for obtaining digital signatures and public-key cryptosystems. Comm. ACM. Vol. 21:1978;120-126.
8. Walter C.D. Systolic modular multiplication. IEEE Trans. Comput. Vol. 42:1993;376-379.