An efficient partitioning algorithm of combinational CMOS circuits

Proceedings of IEEE Computer Society Annual Symposium on VLSI, ISVLSI

Volumn 2002-January, Issue , 2002, Pages 159-164

  Shaer, B ^a   Dib, K ^a  

^a UNIVERSITY OF MINNESOTA DULUTH   (United States)

Author keywords

Circuit faults; Circuit testing; CMOS integrated circuits; CMOS technology; Delay; Electrical fault detection; Fault detection; Partitioning algorithms; Statistical analysis; Very large scale integration

Indexed keywords

ALGORITHMS; AXIAL FLOW; DELAY CIRCUITS; ELECTRIC FAULT LOCATION; ELECTRIC NETWORK ANALYSIS; FAULT DETECTION; INTEGRATED CIRCUIT TESTING; INTEGRATION TESTING; OPTIMIZATION; STATISTICAL METHODS; VLSI CIRCUITS;

CIRCUIT FAULTS; CIRCUIT TESTING; CMOS TECHNOLOGY; DELAY; ELECTRICAL FAULT DETECTIONS; PARTITIONING ALGORITHMS;

CMOS INTEGRATED CIRCUITS;

EID: 84942030025     PISSN: 21593469     EISSN: 21593477     Source Type: Conference Proceeding    
DOI: 10.1109/ISVLSI.2002.1016890     Document Type: Conference Paper

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