Partitioning sequential circuits for pseudoexhaustive testing

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Volumn 8, Issue 5, 2000, Pages 534-541

  Shaer, Bassam ^a   Al Arian, Sami A ^b   Landis, David ^c  

^a UNIVERSITY OF MINNESOTA DULUTH   (United States)

^b University of South Florida   (United States)

^c PENNSYLVANIA STATE UNIVERSITY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; COMPUTER SIMULATION; CONTROLLABILITY; DESIGN FOR TESTABILITY; DIGITAL INTEGRATED CIRCUITS; ELECTRIC NETWORK ANALYSIS; GRAPH THEORY; MULTIPLEXING EQUIPMENT; OBSERVABILITY; SEQUENTIAL CIRCUITS;

ACYCLIC GRAPH; DIGITAL VERY LARGE SCALE INTEGRATION CIRCUITS; FANOUT VALUES; MULTIPLEXERS; PRIMARY INPUT CONES; SEQUENTIAL CIRCUIT TESTING;

INTEGRATED CIRCUIT TESTING;

EID: 0034289944     PISSN: 10638210     EISSN: None     Source Type: Journal    
DOI: 10.1109/92.894159     Document Type: Article

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