Partitioning algorithm to enhance pseudoexhaustive testing of digital VLSI circuits

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Volumn 8, Issue 6, 2000, Pages 750-754

  Shaer, Bassam ^a   Landis, David ^b   Al Arian, Sami A ^c  

^a UNIVERSITY OF MINNESOTA DULUTH   (United States)

^b PENNSYLVANIA STATE UNIVERSITY   (United States)

^c UNIVERSITY OF SOUTH FLORIDA   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; BENCHMARKING; CONTROLLABILITY; DESIGN FOR TESTABILITY; DIGITAL INTEGRATED CIRCUITS; ELECTRIC NETWORK ANALYSIS; INTEGRATED CIRCUIT TESTING; LOGIC DESIGN; MULTIPLEXING EQUIPMENT; OBSERVABILITY;

AUTOMATIC TEST PATTERN GENERATION; MULTIPLEXERS; PARTITIONING ALGORITHM; PRIMARY INPUT CONES AND FANOUT; PSEUDOEXHAUSTIVE TESTING; RECONFIGURABLE TEST CELLS;

VLSI CIRCUITS;

EID: 0034459630     PISSN: 10638210     EISSN: None     Source Type: Journal    
DOI: 10.1109/92.902271     Document Type: Article

References (15)

1. P. Goel, "Test generation costs analysis and projections," in Proc. ACM/IEEE 17th Design Automation Conf., June 1980, pp. 77-84.
2. E. J. McCluskey and S. Bozorgui-Nesbat, "Design for autonomous test," IEEE Trans. Comput., vol. C-30, pp. 866-875, Nov. 1981.
3. M. W. Roberts and P. K. Lala, "An algorithm for the partitioning of logic circuits," Proc. Inst. Elect. Eng. E, vol. 131, no. 4, pp. 113-118, July 1984.
4. W. B. Jone and C. A. Papachristou, "A coordinated approach to partitioning and test pattern generation for pseudoexhaustive testing," in Proc. 26th ACM/IEEE Design Automation Conf., 1989, pp. 525-530.
5. S. Hellebrand, H. J. Wunderlich, and O. F. Haberl, "Generating pseudo-exhaustive vectors for external testing," in Proc. Int. Test Conf., 1990, pp. 670-679.
6. R. Srinivasan, S. K. Gupta, and M. A. Breuer, "Novel test pattern generators for pseudo-exhaustive testing," in Proc. Int. Test Conf., 1993, pp. 1041-1050.
7. D. Kagaris, S. Tragoudas, and D. Bhatia, "Pseudo-exhaustive built-in TPG for sequential circuits," IEEE Trans. Computer-Aided Design, pp. 1160-1171, Sept. 1995.
8. J. G. Udell Jr. and E. J. McCluskey, "Efficient circuit segmentation for pseudoexhaustive test," in Proc. Int. Conf. Computer-Aided Design, 1987, pp. 148-151.
9. K. Kinoshita and K. K. Saluja, "Built-in testing of memory using an on-chip compact scheme," IEEE Trans. Comput., vol. C-35, pp. 862-870, Oct. 1986.
10. C. Y. Liu and K. K. Saluja, "BIST-PLA: A built-in self-test design of large programmable logic arrays," in Proc. Design Automation Conf., 1987, pp. 385-391.
11. B. Shaer, S. Al-Arian, and D. Landis, "Pseudo-exhaustive testing of sequential circuits," in Proc. 9th Great Lakes Symp. VLSI, 1999, pp. 109-112.
12. _, "Partitioning algorithm to enhance VLSI testability," in Proc. 36th ACM Southeast Conf., 1998, pp. 121-129.
13. I. Shperling and E. J. McCluskey, "Circuit segmentation for pseudo-exhaustive testing via simulated annealing," in Proc. Int. Test Conf., 1987, pp. 58-65.
14. F. Brglez, D. Bryan, and K. Kozminski, "Combinational profile of sequential benchmark circuits," in Proc. IEEE Int. Symp. Circuits and Systems, 1989, pp. 1929-1934.
15. S. Al-Arian and R. Bolling, "Improving the testability of VLSI circuits through partitioning," Proc. IEEE Symp. Circuits and Systems, vol. 4, pp. 199-202, 1994.