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Volumn 4, Issue 4, 2015, Pages 235-240

ITRS lithography roadmap: 2015 challenges

Author keywords

Directed self assembly (DSA); EUV lithography; ITRS roadmap; lithography; maskless lithography; multiple patterning; nanoimprint; semiconductor patterning

Indexed keywords


EID: 84941652204     PISSN: 21928576     EISSN: 21928584     Source Type: Journal    
DOI: 10.1515/aot-2015-0036     Document Type: Review
Times cited : (103)

References (25)
  • 3
    • 84907688609 scopus 로고    scopus 로고
    • A 10 Nm platform technology for low power and high performance application featuring finfet devices with multi workfunction gate stack on bulk and soI
    • Honolulu, HI
    • K. Seo, B. Haran, D. Gupta, D. Guo, T. Standaert, et al., A 10 nm Platform Technology for Low Power and High Performance Application Featuring FINFET Devices with Multi Workfunction Gate Stack on Bulk and SOI, 2014 Symposium on VLSI Technology, Honolulu, HI.
    • (2014) Symposium on VLSI Technology
    • Seo, K.1    Haran, B.2    Gupta, D.3    Guo, D.4    Standaert, T.5


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.