Structure of the breakdown spot during progressive breakdown of ultra-thin gate oxides

IEEE International Reliability Physics Symposium Proceedings

Volumn 2004-January, Issue January, 2004, Pages 583-584

  Palumbo, F ^a   Lombardo, S ^a   Pey, K L ^b   Fang, L J ^b,c   Tung, C H ^c   Lin, W H ^d   Radhakrishnan, M K ^e   Falci, G ^f  

^a CNR IMM   (Italy)

^b NANYANG TECHNOLOGICAL UNIVERSITY   (Singapore)

^c INSTITUTE OF MICROELECTRONICS   (Singapore)

^d CHARTERED SEMICONDUCTOR MANUFACTURING LTD   (Singapore)

^e NATIONAL UNIVERSITY OF SINGAPORE   (Singapore)

^f UNIVERSITY OF CATANIA   (Italy)

Author keywords

[No Author keywords available]

Indexed keywords

CMOS INTEGRATED CIRCUITS; MOS DEVICES;

ACCELERATED TESTS; ACCURATE MODELING; OPERATING CONDITION; OPERATING VOLTAGE; PHYSICAL STRUCTURES; PROGRESSIVE BREAKDOWN; QUANTITATIVE MODELING; ULTRA THIN GATE OXIDE;

GATES (TRANSISTOR);

EID: 84932176332     PISSN: 15417026     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/RELPHY.2004.1315400     Document Type: Conference Paper

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