Analysis and modeling of four-folded vertical Hall devices in current domain

Conference Proceedings - 10th Conference on Ph. D. Research in Microelectronics and Electronics, PRIME 2014

Volumn , Issue , 2014, Pages

  Heidari, Hadi ^a   Bonizzoni, Edoardo ^a   Gatti, Umberto ^a   Maloberti, Franco ^a  

^a UNIVERSITY OF PAVIA   (Italy)

Author keywords

[No Author keywords available]

Indexed keywords

MICROELECTRONICS;

ANALYSIS AND MODELING; CURRENT MODE; DIFFERENT GEOMETRY; ELECTRICAL BEHAVIORS; HALL DEVICES; SPINNING TECHNIQUE; VERILOG-A MODELS; VERTICAL HALL SENSORS;

HALL EFFECT TRANSDUCERS;

EID: 84929340291     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/prime.2014.6872733     Document Type: Conference Paper

References (7)

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3. O. Paul, R. Raz, and T. Kaufmann, "Analysis of the offset of semiconductor vertical hall devices," Sensors and Actuators A: Physical, vol. 174, pp. 24-32, 2012.
4. G.-M. Sung and C.-P. Yu, "2-d difierential folded vertical hall device fabricated on a p-Type substrate using cmos technology," IEEE Sensors Journal, vol. 13, no. 6, pp. 2253-2262, June 2013.
5. C. Sander, R. Raz, P. Ruther, O. Paul, T. Kaufmann, M. Cornils, and M. Vecchi, "Fully symmetric vertical hall devices in cmos technology," in Proc. Of IEEE Sensors, Nov 2013, pp. 1-4.
6. E. Schurig, "Highly sensitive vertical hall sensors in cmos technology," Ph.D. dissertation, EPFL, 2005. [Online]. Available: Http://infoscience.epfl.ch/record/33603
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