A new memetic algorithm with fitness approximation for the defect-tolerant logic mapping in crossbar-based nanoarchitectures

IEEE Transactions on Evolutionary Computation

Volumn 18, Issue 6, 2014, Pages 846-859

  Yuan, Bo ^a   Li, Bin ^a   Weise, Thomas ^a   Yao, Xin ^b  

^a UNIVERSITY OF SCIENCE AND TECHNOLOGY OF CHINA   (China)

^b UNIVERSITY OF BIRMINGHAM   (United Kingdom)

Author keywords

crossbar based nanoelectronics; defect tolerant logic mapping (DTLM); fitness approximation; local search; maximum bipartite matching (MBM); Memetic algorithms

Indexed keywords

APPROXIMATION ALGORITHMS; BENCHMARKING; COMBINATORIAL OPTIMIZATION; COMPUTATION THEORY; COMPUTER CIRCUITS; EFFICIENCY; EVOLUTIONARY ALGORITHMS; HEALTH; LOCAL SEARCH (OPTIMIZATION); MAPPING; PROBLEM SOLVING;

BIPARTITE MATCHINGS; FITNESS APPROXIMATION; LOCAL SEARCH; LOGIC MAPPING; MEMETIC ALGORITHMS;

OPTIMIZATION;

EID: 84914097965     PISSN: 1089778X     EISSN: None     Source Type: Journal    
DOI: 10.1109/TEVC.2013.2288779     Document Type: Article

References (40)

1. G. Bourianoff, J. E. Brewer, R. Cavin, J. A. Hutchby, and V. Zhirnov, "Boolean logic and alternative information-processing devices," Computer, vol. 41, no. 5, pp. 38-46, May 2008.
2. R. Cavin, J. A. Hutchby, V. Zhirnov, J. E. Brewer, and G. Bourianoff, "Emerging research architectures," Computer, vol. 41, no. 5, pp. 33-37, May 2008.
3. H. Yan, H. S. Choe, S. W. Nam, Y. Hu, S. Das, J. F. Klemic, et al., "Programmable nanowire circuits for nanoprocessors," Nature, vol. 470, pp. 240-244, Feb. 2011.
4. W. Lu and C. M. Lieber, "Nanoelectronics from the bottom up," Nat. Mater., vol. 6, no. 11, pp. 841-850, Nov. 2007.
5. Y. Chen, G.-Y. Jung, D. A. A. Ohlberg, X. M. Li, D. R. Stewart, J. O. Jeppesen, et al., "Nanoscale molecular-switch crossbar circuits," Nanotechnology, vol. 14, no. 4, pp. 462-468, Apr. 2003.
6. M. Haselman and S. Hauck, "The future of integrated circuits: A survey of nanoelectronics," Proc. IEEE, vol. 98, no. 1, pp. 11-38, Jan. 2010.
7. A. DeHon and H. Naeimi, "Seven strategies for tolerating highly defective fabrication," IEEE Des. Test Comput., vol. 22, no. 4, pp. 306-315, Jul./Aug. 2005.
8. T. Hogg and G. Snider, "Defect-tolerant adder circuits with nanoscale crossbars," IEEE Trans. Nanotechnol., vol. 5, no. 2, pp. 97-100, Mar. 2006.
9. T. Hogg and G. Snider, "Defect-tolerant logic with nanoscale crossbar circuits," J. Electr. Testing Theor. Appl., vol. 23, nos. 2-3, pp. 117-129, Jun. 2007.
10. Y. Yellambalase and M. Choi, "Cost-driven repair optimization of reconfigurable nanowire crossbar systems with clustered defects," J. Syst. Archit., vol. 54, no. 8, pp. 729-741, Aug. 2008.
11. W. Rao, A. Orailoglu, and R. Karri, "Logic mapping in crossbar-based nanoarchitectures," IEEE Des. Test Comput., vol. 26, no. 1, pp. 68-76, Jan. 2009.
12. M. B. Tahoori, "Application-independent defect tolerance of reconfigurable nanoarchitectures," ACM J. Emerging Technol. Comput. Syst., vol. 2, no. 3, pp. 197-218, Jul. 2005.
13. A. Al-Yamani, S. Ramsundar, and D. K. Pradham, "A defect tolerance scheme for nanotechnology circuits," IEEE Trans. Circuits Syst. I, Reg. Pappers, vol. 54, no. 11, pp. 2402-2409, Nov. 2007.
14. M. S. Garey and D. S. Johnson, Computers and Intractibility: A Guide to NP-Completeness. New York, NY, USA: Freeman, 1979.
15. J. R. Ullmann, "An algorithm for subgraph isomorphism," J. Assoc. Comput. Mach., vol. 23, no. 1, pp. 31-42, Jan. 1976.
16. L. P. Cordella, P. Foggia, C. Sansone, and M. Vento, "A (sub)graph isomorphism algorithm for matching large graphs," IEEE Trans. Pattern Anal. Mach. Intell., vol. 26, no. 10, pp. 1367-1372, Oct. 2004.
17. M. O. Simsir, S. Cadamibi, F. Ivancic, M. Roetteler, and N. K. Jha, "A hybrid nano-CMOS architecture for defect and fault tolerance," ACM J. Emerging Technol. Comput. Syst., vol. 5, no. 3, Aug. 2009.
18. S. Goren, H. F. Ugurdag, and O. Palaz, "Defect-aware nanocrossbar logic mapping through matrix canonization using 2-D radix sort," ACM J. Emerging Technol. Comput. Syst., vol. 7, no. 3, article 12, Aug. 2011.
19. N. Krasnogor and J. Smith, "A tutorial for competent memetic algorithms: Model, taxonomy, and design issues," IEEE Trans. Evol. Comput., vol. 9, no. 5, pp. 474-488, Oct. 2005.
20. X. S. Chen, Y. S. Ong, M. H. Lim, and K. C. Tan, "A multi-facet survey on memetic computation," IEEE Trans. Evol. Comput., vol. 15, no. 5, pp. 591-607, Oct. 2011.
21. M. Tang and X. Yao, "A memetic algorithm for VLSI floorplanning," IEEE Trans. Syst., Man, Cybern. B, Cybern., vol. 37, no. 1, pp. 62-69, Feb. 2007.
22. T. H. Cormen, C. E. Leiserson, R. L. Rivest, and C. Stein, Introduction to Algorithms. Cambridge, MA, USA: MIT Press, 2001.
23. A. DeHon, "Nanowire-based programmable architectures," ACM J. Emerging Technol. Comput. Syst., vol. 1, no. 2, pp. 109-162, Jul. 2005.
24. J. Dai, L. Wang, and F. Jain, "Analysis of defect tolerance in molecular crossbar electronics," IEEE Trans. Very Large Scale Integration (VLSI) Syst., vol. 17, no. 4, pp. 529-540, Apr. 2009.
25. M. Crocker, X. S. Hu, and M. Niemier, "Defects and faults in QCAbased PLAs," ACM J. Emerging Technol. Comput. Syst., vol. 5, no. 2, Article 8, Jul. 2009.
26. E. M. Luks, "Isomorphism of graphs of bounded valence can be tested in polynomial time," J. Comput. Syst. Sci., vol. 25, no. 1, pp. 42-65, Aug. 1982.
27. J. He and X. Yao, "Maximum cardinality matching by evolutionary algorithms," in Proc. U.K. Workshop Comput. Intell., Sep. 2002, pp. 53-60.
28. Y. Zheng and C. Huang, "Defect-aware logic mapping for nanowirebased programmable logic arrays via satisfiability," in Proc. Conf. Design Autom. Test Eur., Apr. 2009, pp. 1279-1283.
29. C. Tune and M. B. Tahoori, "Variation tolerant logic mapping for crossbar array nano architectures," in Proc. 15th Asia South Pacific Design Autom. Conf., Jan. 2010, pp. 858-860.
30. B. Yuan and B. Li, "Coverage optimization for defect-tolerant logic mapping on nanoelectronic crossbar architectures," J. Comput. Sci. Technol., vol. 27, no. 5, pp. 979-988, Sep. 2012.
31. P. Merz and F. Bernd, "Fitness landscape analysis and memetic algorithms for the quadratic assignment problem," IEEE Trans. Evol. Comput., vol. 4, no. 4, pp. 337-352, Nov. 2000.
32. S. Salcedo-Sanz and X. Yao, "A hybrid hopfield network-genetic algorithm approach for the terminal assignment problem," IEEE Trans. Syst., Man, Cybern. B, Cybern., vol. 34, no. 6, pp. 2343-2353, Dec. 2004.
33. S. Salcedo-Sanz, Y. Xu, and X. Yao, "Hybrid meta-heuristics algorithms for task assignment in heterogeneous computing systems," Comput. Oper. Res., vol. 33, no. 3, pp. 820-835, Mar. 2006.
34. H. Lau, T. M. Chan, and W. T. Tsui, "Item-location assignment using fuzzy logic guided genetic algorithms," IEEE Trans. Evol. Comput., vol. 12, no. 6, pp. 765-780, Dec. 2008.
35. C. F. T. Soares, A. C. de Mesquita Filho, and A. Petraglia, "Optimizing capacitance ratio assignment for low-sensitivity SC filter implementation," IEEE Trans. Evol. Comput., vol. 14, no. 3, pp. 375-380, Jun. 2010.
36. K.-H. Liang, X. Yao, and C. Newton, "Evolutionary search of approximated N-dimensional landscapes," Int. J. Knowledge-Based Intell. Eng. Syst., vol. 4, no. 3, pp. 172-183, Jul. 2000.
37. E. S. Buffa, G. C. Armour, and T. E. Vollmann, "Allocating facilities with CRAFT," Harvard Business Rev., vol. 42, pp. 136-158, Mar. 1964.
38. Y. Jin, "A comprehensive survey of fitness approximation in evolutionary computation," Soft Comput., vol. 9, no. 1, pp. 3-12, Jan. 2005.
39. Y. Jin, M. Olhofer, and B. Sendhoff, "A framework for evolutionary optimization with approximate fitness functions," IEEE Trans. Evol. Comput., vol. 6, no. 5, pp. 481-494, Oct. 2002.
40. Y. Su and W. Rao, "Runtime analysis for defect-tolerant logic mapping on nanoscale crossbar architectures," in Proc. IEEE/ACM Int. Symp. Nanoscale Architectures, Jul. 2009, pp. 75-78.