Investigation of performance improvement and gate-to-junction leakage reduction for the 90nm CMOS gate stack architecture

European Solid-State Device Research Conference

Volumn , Issue , 2002, Pages 563-566

  Henson, K ^a   Kubicek, S ^a   Redolfi, A ^a   De Meyer, K ^a,b   Jurczak, M ^a   Augendre, E ^a  

^a IMEC   (Belgium)

^b UNIVERSITY OF LEUVEN   (Belgium)

Author keywords

[No Author keywords available]

Indexed keywords

DRIVE CURRENTS; GATE LENGTH; INVERTER DELAY; LEAKAGE REDUCTION; OPERATING VOLTAGE; PMOS TRANSISTORS; STATE OF THE ART; SWITCHING CHARACTERISTICS;

LOGIC GATES;

EID: 84907697337     PISSN: 19308876     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ESSDERC.2002.194993     Document Type: Conference Paper

References (3)

1. M. Cao et al, "Boron Diffusion and Penetration in Ultrathin Oxide with Poly-Si Gate," IEEE Electron Device Letters, vol 19, 1998, pp. 291 - 293.
2. B. Yu et al, "CMOS Transistor Reliability and Performance Impacted by Gate Microstruture," 1997 IEEE International Integrated Reliability Workshop Final Report, p. 35.
3. Ghani et al, "100nm Gate Length High Performance /Low Power CMOS Transistor Structure," 1999 Int. Electron Device Meeting, Washington DC, pp. 415- 418.