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Volumn , Issue , 2014, Pages 476-487

Improving in-memory database index performance with Intel® Transactional Synchronization Extensions

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER ARCHITECTURE; DATA STRUCTURES; FORESTRY; HARDWARE; QUERY PROCESSING; SUPERCOMPUTERS; SYNCHRONIZATION;

EID: 84903981111     PISSN: 15300897     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/HPCA.2014.6835957     Document Type: Conference Paper
Times cited : (54)

References (24)
  • 1
    • 84904006621 scopus 로고    scopus 로고
    • Intel 64 and IA-32 Architectures Optimization Reference Manual. 2013. Intel Corporation
    • Intel 64 and IA-32 Architectures Optimization Reference Manual. 2013. Intel Corporation.
  • 2
    • 84904006623 scopus 로고    scopus 로고
    • Intel 64 and IA-32 Architectures Software Developer Manual. 2013. Intel Corporation
    • Intel 64 and IA-32 Architectures Software Developer Manual. 2013. Intel Corporation.
  • 10
    • 77955207233 scopus 로고    scopus 로고
    • A survey of B-tree locking techniques
    • G. Graefe. A Survey of B-Tree Locking Techniques. ACM Trans. Database Syst., 35(3), 2010.
    • (2010) ACM Trans. Database Syst. , vol.35 , Issue.3
    • Graefe, G.1
  • 14
    • 84904016005 scopus 로고    scopus 로고
    • Is transactional memory an oxymoron?
    • Aug.
    • M. D. Hill. Is Transactional Memory an Oxymoron? Proceedings of the VLDB Endowment, 1(1):1-1, Aug. 2008.
    • (2008) Proceedings of the VLDB Endowment , vol.1 , Issue.1 , pp. 1-1
    • Hill, M.D.1
  • 16
    • 0019666493 scopus 로고
    • Efficient locking for concurrent operations on B-trees
    • P. L. Lehman and S. B. Yao. Efficient Locking for Concurrent Operations on B-trees. ACM Trans. Database Syst., 1981.
    • (1981) ACM Trans. Database Syst.
    • Lehman, P.L.1    Yao, S.B.2
  • 22
    • 84860598151 scopus 로고    scopus 로고
    • PALM: Parallel architecture-friendly latch-free modifications to B+ trees on many-core processors
    • J. Sewall, J. Chhugani, C. Kim, N. R. Satish, and P. Dubey. PALM: Parallel Architecture-Friendly Latch-Free Modifications to B+ Trees on Many-Core Processors. Proceedings of the VLDB Endowment, 4(11):795-806, 2011.
    • (2011) Proceedings of the VLDB Endowment , vol.4 , Issue.11 , pp. 795-806
    • Sewall, J.1    Chhugani, J.2    Kim, C.3    Satish, N.R.4    Dubey, P.5


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.