Bus designs for time-probabilistic multicore processors

Proceedings -Design, Automation and Test in Europe, DATE

Volumn , Issue , 2014, Pages

  Jalle, Javier ^a,b   Kosmidis, Leonidas ^a,b   Abella, Jaume ^b   Quinoñes, Eduardo ^b   Cazorla, Francisco J ^b,c  

^a UNIVERSITAT POLITÈCNICA DE CATALUNYA   (Spain)

^b BARCELONA SUPERCOMPUTING CENTER   (Spain)

^c ARTIFICIAL INTELLIGENCE RESEARCH INSTITUTE IIIA CSIC   (Spain)

Author keywords

[No Author keywords available]

Indexed keywords

BUSES; COST BENEFIT ANALYSIS; HARDWARE; REAL TIME SYSTEMS;

AMOUNT OF INFORMATION; GUARANTEED PERFORMANCE; HARDWARE COST; HARDWARE DESIGN; MULTI-CORE PROCESSOR; MULTI-CORES; SINGLE-CORE PROCESSORS; TIMING ANALYSIS;

DESIGN;

EID: 84903832984     PISSN: 15301591     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.7873/DATE2014.063     Document Type: Conference Paper

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