Silicon nanowire fabrication: Silicon trimming via shallow anisotropic etching

Microelectronics International

Volumn 31, Issue 2, 2014, Pages 78-85

  Adam, Tijjani ^a   Hashim, U ^a  

^a UNIVERSITY MALAYSIA PERLIS   (Malaysia)

Author keywords

Anisotropic; Current voltage; Etching; ICP RIE; Photolithography; Semiconductor; Shallow; Silicon; Silicon on insulator; Trimming

Indexed keywords

ANISOTROPIC ETCHING; ATOMIC FORCE MICROSCOPY; ETCHING; FABRICATION; INDUCTIVELY COUPLED PLASMA; NANOWIRES; PHOTOLITHOGRAPHY; PHOTORESISTS; SCANNING ELECTRON MICROSCOPY; SEMICONDUCTOR MATERIALS; SILICON; SILICON ON INSULATOR TECHNOLOGY; SILICON OXIDES; TRIMMING; WIRE;

ANISOTROPIC; CONVENTIONAL PHOTOLITHOGRAPHY; CURRENT VOLTAGE; DESIGN/METHODOLOGY/APPROACH; ICP-RIE; INDUCTIVELY COUPLED PLASMA (ICP); MORPHOLOGICAL CHARACTERIZATION; SHALLOW;

SILICON WAFERS;

EID: 84902820512     PISSN: 13565362     EISSN: None     Source Type: Journal    
DOI: 10.1108/MI-10-2013-0055     Document Type: Article

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