Compact FPGA-based true and pseudo random number generators

IEEE Symposium on FPGAs for Custom Computing Machines, Proceedings

Volumn 2003-January, Issue , 2003, Pages 51-61

  Tsoi, K H ^a   Leung, K H ^a   Leong, P H W ^a  

^a CHINESE UNIVERSITY OF HONG KONG   (Hong Kong)

Author keywords

Bit rate; Field programmable gate arrays; Hardware; Oscillators; Phase noise; Polynomials; Public key cryptography; Random number generation; Testing; Very large scale integration

Indexed keywords

COMPUTER HARDWARE; COMPUTERS; CRYPTOGRAPHY; FIELD PROGRAMMABLE GATE ARRAYS (FPGA); HARDWARE; INTEGRATION TESTING; LOGIC GATES; NUMBER THEORY; OSCILLATORS (ELECTRONIC); PHASE NOISE; POLYNOMIALS; PROGRAMMABLE LOGIC CONTROLLERS; PUBLIC KEY CRYPTOGRAPHY; SIGNAL RECEIVERS; TESTING; VLSI CIRCUITS;

BIT RATES; BIT SERIAL IMPLEMENTATION; CRYPTOGRAPHIC APPLICATIONS; CRYPTOGRAPHIC HARDWARE; OSCILLATOR PHASE NOISE; PSEUDO RANDOM NUMBER GENERATORS; RANDOM NUMBER GENERATORS; RANDOM NUMBERS;

RANDOM NUMBER GENERATION;

EID: 84899682129     PISSN: 10823409     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/FPGA.2003.1227241     Document Type: Conference Paper

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