Chaos-based random number generators - Part II: Practical realization

IEEE Transactions on Circuits and Systems I: Fundamental Theory and Applications

Volumn 48, Issue 3, 2001, Pages 382-385

  Stojanovski, Toni ^a   Pihl, Johnny ^b   Kocarev, Ljupčo ^c  

^a Expert Information Services   (Australia)

^b NORWEGIAN UNIVERSITY OF SCIENCE AND TECHNOLOGY   (Norway)

^c UNIVERSITY OF CALIFORNIA   (United States)

Author keywords

Chaos; CMOS; Random number generator

Indexed keywords

BIT ERROR RATE; CHAOS THEORY; CMOS INTEGRATED CIRCUITS; PIECEWISE LINEAR TECHNIQUES; REDUNDANCY; SWITCHING CIRCUITS;

OUTPUT BIT RATE; PARASITIC ATTRACTORS;

RANDOM NUMBER GENERATION;

EID: 0035272651     PISSN: 10577122     EISSN: None     Source Type: Journal    
DOI: 10.1109/81.915396     Document Type: Article

References (5)

1. Chaos based random number generators part I: Analysis
2. Application of chaotic switched-capacitor circuits for random-number generation
3. Secure random number generation using chaotic circuits
4. Nonlinear switched-current CMOS IC for random signal generation