Tradeoffs in parallel and serial implementations of the international data encryption algorithm IDEA

Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)

Volumn 2162, Issue , 2001, Pages 333-347

  Cheung, O ^a   Tsoi, K H ^a   Leong, P ^a   Leong, M P ^a  

^a CHINESE UNIVERSITY OF HONG KONG   (Hong Kong)

Author keywords

Cryptographic hardware; Digital design; Performance tradeoffs; Reconfigurable computing

Indexed keywords

COMMERCE; COMPUTATION THEORY; COMPUTER HARDWARE; EMBEDDED SYSTEMS; FIELD PROGRAMMABLE GATE ARRAYS (FPGA); HIGH SPEED NETWORKS; INTEGRATED CIRCUIT DESIGN; RECONFIGURABLE ARCHITECTURES; RECONFIGURABLE HARDWARE; SCHEDULING;

AND INTERNATIONAL DATA ENCRYPTION ALGORITHMS (IDEA); CRYPTOGRAPHIC HARDWARE; DIGITAL DESIGNS; HIGH PERFORMANCE IMPLEMENTATIONS; INTERNATIONAL DATA ENCRYPTION ALGORITHMS; PERFORMANCE TRADE-OFF; RECONFIGURABLE COMPUTING; RUN-TIME RECONFIGURABLE;

CRYPTOGRAPHY;

EID: 79957587246     PISSN: 03029743     EISSN: 16113349     Source Type: Book Series    
DOI: 10.1007/3-540-44709-1_28     Document Type: Conference Paper

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