A 1GS/s 10b 18.9mW time-interleaved SAR ADC with background timing-skew calibration

Digest of Technical Papers - IEEE International Solid-State Circuits Conference

Volumn 57, Issue , 2014, Pages 384-385

  Lee, Sunghyuk ^a   Chandrakasan, Anantha P ^a   Lee, Hae Seung ^a  

^a MASSACHUSETTS INSTITUTE OF TECHNOLOGY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

BANDWIDTH; CALIBRATION; ERRORS;

CONVERSION SPEED; ENERGY EFFICIENT; ERROR SOURCES; LIMITED BANDWIDTH; SAR ADC; SIGNAL FREQUENCIES; TIME-INTERLEAVED; TIMING REFERENCES;

ANALOG TO DIGITAL CONVERSION;

EID: 84898075382     PISSN: 01936530     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ISSCC.2014.6757480     Document Type: Conference Paper

References (6)

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2. H. Hong, et al. "An 8.6 ENOB 900MS/s Time-Interleaved 2b/cycle SAR ADC with a 1b/cycle Reconfiguration for Resolution Enhancement," ISSCC Dig. Tech. Papers, pp. 470-471, Feb. 2013.
3. M. El-Chammas and B. Murmann, "A 12-GS/s 81-mW 5-bit Time-Interleaved Flash ADC With Background Timing Skew Calibration," IEEE J. Solid-State Circuits, vol. 46, no. 4, pp. 838-847, Apr. 2011.
4. B. Sung, et al. "A Time-Interleaved Flash-SAR Architecture for High Speed A/D Conversion," Proc. IEEE ISCAS, pp. 984-987, May 2009.
5. S. H. Lewis and P. R. Gray, "A Pipelined 5-Msample/s 9-bit Analog-to-Digital Converter," IEEE J. Solid-State Circuits, vol. 22, no. 6, pp. 954-961, Dec. 1987.
6. S.-W. Chen and R. Brodersen, "A 6b 600MS/s 5.3mW Asynchronous ADC in 0.13μm CMOS," ISSCC Dig. Tech. Papers, pp. 574-575, Feb. 2006.