A time-interleaved flash-SAR architecture for high speed A/D conversion

Proceedings - IEEE International Symposium on Circuits and Systems

Volumn , Issue , 2009, Pages 984-987

  Sung, Ba Ro Saim ^a   Cho, Sang Hyun ^a   Lee, Chang Kyo ^a   Kim, Jong In ^a   Ryu, Seung Tak ^a  

^a Korea Advanced Institute of Science and Technology (KAIST)   (South Korea)

Author keywords

[No Author keywords available]

Indexed keywords

A/D CONVERSION; BEHAVIORAL MODEL; CIRCUIT DESIGNS; FLASH-ADC; FRONT END; HIGH SPEED ADC; LOW RESOLUTION; NUMBER OF CYCLES; POWER EFFICIENT; SAMPLING NETWORK; SAR ADC; TIME-INTERLEAVED;

ANALOG TO DIGITAL CONVERSION; INTEGRATED CIRCUIT MANUFACTURE; SYNTHETIC APERTURES;

MULTICARRIER MODULATION;

EID: 70350166452     PISSN: 02714310     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ISCAS.2009.5117923     Document Type: Conference Paper

References (5)

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3. Zhiheg Cao, Shouli Yan, Yunchu Li, "A 32mW 1.25GS/s 6b 2b/step SAR ADC in 0.13μm CMOS," in IEEE Conf. ISSCC Dig.Tech. papers, pp.542-543, Feb. 2008.
4. Pedro M. Figueiredo, Paulo Cardoso, Ana Lopes, Carlos Fachada, Naoyuki Hamanishi, Ken Tanabe, João Vital "A 90nm CMOS 1.2V 6b 1GS/s Two-Step Subranging ADC," in IEEE Conf. ISSCC Dig.Tech. papers, pp.568-569, Feb. 2006.
5. Brian P. Ginsburg, Anantha P. Chandrakasan, "Dual Time-Interleaved Successive Approximation Register ADCs for an Ultra-Wideband Receiver," in IEEE J. Solid-State Circuit, vol. 42, No. 2, pp.247-257, Feb.2007