An 8.6 ENOB 900MS/s time-interleaved 2b/cycle SAR ADC with a 1b/cycle reconfiguration for resolution enhancement

Digest of Technical Papers - IEEE International Solid-State Circuits Conference

Volumn 56, Issue , 2013, Pages 470-471

  Hong, Hyeok Ki ^a   Kang, Hyun Wook ^a   Sung, Barosaim ^a   Lee, Choong Hoon ^b   Choi, Michael ^b   Park, Ho Jin ^b   Ryu, Seung Tak ^a  

^a Korea Advanced Institute of Science and Technology (KAIST)   (South Korea)

^b SAMSUNG Electronics   (South Korea)

Author keywords

[No Author keywords available]

Indexed keywords

CIRCUIT COMPLEXITY; CONVERSION RATES; DESIGN TECHNIQUE; HARDWARE OVERHEADS; LIMITED RESOLUTION; LOW-POWER CONSUMPTION; RESOLUTION ENHANCEMENT; TIME-INTERLEAVED;

COMPARATORS (OPTICAL); ELECTRIC CONVERTERS; ERRORS; HARDWARE;

ANALOG TO DIGITAL CONVERSION;

EID: 84876574678     PISSN: 01936530     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ISSCC.2013.6487819     Document Type: Conference Paper

References (6)

1. C.-H. Chan, et al., "A 3.8mW 8b 1GS/s 2b/cycle Interleaving SAR ADC with Compact DAC Structure," Symp. VLSI Circuits, pp. 86-87, June 2012
2. Y.-C. Lien, "A 4.5-mW 8-b 750-MS/s 2-b/step Asynchronous Subranged SAR ADC in 28-nm CMOS Technology," Symp. VLSI Circuits, pp. 88-89, June 2012
3. H.-K. Hong, et al., "A 7b 1GS/s 7.2mW Nonbinary 2b/cycle SAR ADC with Register-To-DAC Direct Control," IEEE CICC, Sept. 2012
4. Y. Zhu, et al. "A 34fJ 10b 500 MS/s Partial-Interleaving Pipelined SAR ADC," Symp. VLSI Circuits, pp. 90-91, June 2012
5. Z. Cao, S. Yan, and Y. Li, "A 32mW 1.25GS/s 6b 2b/step SAR ADC in 0.13mm CMOS," ISSCC Dig. Tech. Papers, pp. 542-543, Feb. 2008
6. C.-C. Liu, S.-J. Chang, G.-Y. Huang, and Y.-Z. Lin, "A 10-bit 50-MS/s SAR ADC With a Monotonic Capacitor Switching Procedure," IEEE J. Solid-State Circuits, vol. 45, pp. 731-740, Apr. 2010