A 1TOPS/W analog deep machine-learning engine with floating-gate storage in 0.13µm CMOS

Digest of Technical Papers - IEEE International Solid-State Circuits Conference

Volumn 57, Issue , 2014, Pages 504-505

  Lu, Junjie ^a   Young, Steven ^a   Arel, Itamar ^a   Holleman, Jeremy ^a  

^a UNIVERSITY OF TENNESSEE   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

DIGITAL COMPUTERS; DIGITAL DEVICES; DIGITAL STORAGE; ENERGY EFFICIENCY; FEATURE EXTRACTION; VIDEO SIGNAL PROCESSING;

AUTOMATED FEATURE EXTRACTION; CURSE OF DIMENSIONALITY; HIGH DIMENSIONAL DATA; LEARNING CAPABILITIES; LEARNING TASKS; MACHINE-LEARNING; ON-LINE ADAPTATION; SIGNAL PROCESSOR;

LEARNING SYSTEMS;

EID: 84898062031     PISSN: 01936530     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ISSCC.2014.6757532     Document Type: Conference Paper

References (6)

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3. J.-Y. Kim, et al., "A 201.4GOPS 496mW Real-Time Multi-Object Recognition Processor With Bio-Inspired Neural Perception Engine," ISSCC Dig. Tech. Papers, pp. 150-151, Feb. 2009.
4. S. Chakrabartty and G. Cauwenberghs, "Sub-Microwatt Analog VLSI Trainable Pattern Classifier," IEEE J. Solid-State Circuits, vol. 42, no. 5, pp. 1169-1179, May 2007.
5. J. Lu, et al., "An Analog Online Clustering Circuit in 130nm CMOS," IEEE Asian Solid-State Circuits Conference, Nov. 2013.
6. S. Young, et al., "Hierarchical Spatiotemporal Feature Extraction using Recurrent Online Clustering," Pattern Recognition Letters, Oct. 2013.