A 646GOPS/W multi-classifier many-core processor with cortex-like architecture for super-resolution recognition

Digest of Technical Papers - IEEE International Solid-State Circuits Conference

Volumn 56, Issue , 2013, Pages 168-169

  Park, Junyoung ^a   Hong, Injoon ^a   Kim, Gyeonghoon ^a   Kim, Youchang ^a   Lee, Kyuho ^a   Park, Seongwook ^a   Bong, Kyeongryeol ^a   Yoo, Hoi Jun ^a  

^a Korea Advanced Institute of Science and Technology (KAIST)   (South Korea)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTATIONAL REQUIREMENTS; CONTEXT-AWARE FEATURES; HIERARCHICAL ARCHITECTURES; HUMAN VISION SYSTEMS; MANY-CORE PROCESSORS; MULTICLASSIFIER SYSTEM; SUPER RESOLUTION ALGORITHMS; UNMANNED AIR VEHICLE (UAVS);

COMPUTER VISION; OBJECT RECOGNITION; OPTICAL RESOLVING POWER; TEMPLATE MATCHING; UNMANNED AERIAL VEHICLES (UAV);

COMPUTER ARCHITECTURE;

EID: 84876566153     PISSN: 01936530     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ISSCC.2013.6487685     Document Type: Conference Paper

References (9)

1. J.-Y. Kim, et al., "A 201.4GOPS 496mW Real-Time Multi-Object Recognition Processor with Bio-Inspired Neural Perception Engine," ISSCC Dig. Tech, Papers, pp. 150-151, 2009.
2. S, Lee, et al., "A 345mW Heterogeneous Many-Core Processor with an Intelligent Inference Engine for Robust Object Recognition," ISSCC Dig. Tech, Papers, pp. 332-333, 2010.
3. J. Oh, et al., "A 320mW 342GOPS Real-Time Moving Object Recognition Processor for HD 720p Video Streams," ISSCC Dig. Tech. Papers, pp. 220-221, 2012.
4. Ho, T.K., Hull, J.J., Srihari, S.N., "On multiple classifier systems for pattern recognition," Pattern Recognition, vol. 2. pp. 84-87, 1992.
5. M. Riesenhuber and T. Poggio, "Hierarchical models of object recognition in cortex," Nature Neuroscience, vol. 2, pp. 1019-1025, 1999.
6. D.G. Lowe, "Distinctive image features from scale-invariant keypoints," Intenational Journal of Computer Vision, vol. 60, no. 2, pp. 91-110, 2004.
7. H.-J.Yoo, et al., "Low-Power NoC for High-Performance SoC Design," CRC Press, 2008.
8. Y. Tanabe, et al., "A 464GOPS 620GOPS/W Heterogeneous Multi-Core SoC for Image-Recognition Applications," ISSCC Dig. Tech. Papers, pp. 222-223, 2012.
9. T. Kurafuji, et al., "A Scalable Massively Parallel Processor for Real-Time Image Processing," ISSCC Dig. Tech. Papers, pp. 334-335, 2010.