Interconnect tuning strategies for high-performance ICs

Design, Automation, and Test in Europe: The Most Influential Papers of 10 Years Date

Volumn , Issue , 2008, Pages 359-375

  Kahng, Andrew B ^a   Muddu, Sudhakar ^a   Sarto, Egino ^a   Sharma, Rahul ^a  

^a HEWLETT PACKARD ENTERPRISE   (United States)

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[No Author keywords available]

Indexed keywords

EID: 84895214938     PISSN: None     EISSN: None     Source Type: Book    
DOI: 10.1007/978-1-4020-6488-3_26     Document Type: Chapter

References (13)

1. Semiconductor Industry Association, National Technology Roadmap for Semiconductors, December 1997.
2. A. Deutsch, G. V. Kopcsay, C. W. Surovic, B. J. Rubin, L. M. Terman, R. P. Dunne and T. Gallo, Modeling and Characterization of Long On-chip Interconnections for High-Performance Microprocessors, final report, ARPA HSCD Contract C-556003, September 1995.
3. Also appeared in IBM Journal of Research and Development 39(5), September 1995, 547-567.
4. P. D. Fisher, Clock Cycle Estimations for Future Microprocessor Generations, Proc. IEEE Innovative Systems in Silicon, Austin, October 1997.
5. L. Gwennap, IC Makers Confront RC Limitations, Microdesign Resources Microprocessor Report, August 4, 1997, pp. 14-18.
6. D. P. La Potin, U. Ghoshal, E. Chiprout and S. R. Nassif, Physical Design Challenges for Performance, International Symposium on Physical Design, April 1997, pp. 225-226.
7. J. Meindl, GigaScale Integration: 'Is the Sky the Limit'?, Keynote presentation slides, Hot Chips IX, Stanford, CA, August 25-26, 1997.
8. L. Scheffer, A Roadmap of CAD Tool Changes for Sub-micron Interconnect Problems, International Symposium on Physical Design, April 1997, pp. 104-109.
9. R. F. Sechler, Interconnect design with VLSI CMOS, IBM Journal of Research and Development, January-March 1995, 23-31.
10. J. Cong, L. He, A. B. Kahng, D. Noice, N. Shirali and S. H.-C. Yen, Analysis and Justification of a Simple, Practical 2 1/2-D Capacitance Extraction Methodology, Proc. Design Automation Conference, June 1997.
11. L. Gwennap, IC Vendors Prepare for 0.25-Micron Leap, Microprocessor Report, September 16, 1996, pp. 11-15.
12. A. B. Kahng and S. Muddu, Efficient gate Delay Modeling for Large Interconnect Loads, Proc. IEEE Multi-Chip Module Conf., February 1996.
13. S.-Y. Oh, K.-J. Chang, N. Chang and K. Lee, Interconnect modeling and design in high-speed VLSI/ULSI systems, Proc. International Conference on Computer Design: VLSI in Computers and Processors, October 1992, pp. 184-189.