An FPGA-based fully synchronized design of a bilateral filter for real-time image denoising

IEEE Transactions on Industrial Electronics

Volumn 61, Issue 8, 2014, Pages 4093-4104

  Gabiger Rose, Anna ^a   Kube, Matthias ^b   Weigel, Robert ^a   Rose, Richard ^a  

^a UNIVERSITY OF ERLANGEN NUREMBERG   (Germany)

^b FRAUNHOFER INSTITUTE FOR INTEGRATED CIRCUITS IIS   (Germany)

Author keywords

Bilateral filter; field programmable gate array (FPGA); image processing; noise reduction; real time processing

Indexed keywords

CLOCKS; FIELD PROGRAMMABLE GATE ARRAYS (FPGA); IMAGE PROCESSING; NOISE ABATEMENT; PIXELS;

BILATERAL FILTERS; FIELD-PROGRAMMABLE GATE ARRAY IMPLEMENTATIONS; FILTER COEFFICIENTS; FILTER COMPONENTS; PIPELINE STRUCTURE; REAL-TIME IMAGES; REALTIME PROCESSING; REGISTER TRANSFER LEVEL;

DESIGN;

EID: 84894601531     PISSN: 02780046     EISSN: None     Source Type: Journal    
DOI: 10.1109/TIE.2013.2284133     Document Type: Article

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