Design and implementation of a pipelined datapath for high-speed face detection using FPGA

IEEE Transactions on Industrial Informatics

Volumn 8, Issue 1, 2012, Pages 158-167

  Jin, Seunghun ^a   Kim, Dongkyun ^b   Nguyen, Thuy Tuong ^b   Kim, Daijin ^c   Kim, Munsang ^d   Jeon, Jae Wook ^b  

^a Samsung Advanced Institute of Technology (SAIT)   (South Korea)

^b Sungkyunkwan University   (South Korea)

^c Pohang University of Science and Technology (POSTECH)   (South Korea)

^d Korea Institute of Science and Technology   (South Korea)

Author keywords

Computer vision; face detection; field programmable gate arrays (FPGAs); integrated circuit design

Indexed keywords

ACCURACY LOSS; AREA EFFICIENCY; BOOSTED CLASSIFIERS; CASCADE CLASSIFIERS; CASCADE OF CLASSIFIERS; CLOCK CYCLES; DATA PATHS; DIFFERENT SCALE; DOWN-SCALING; FULLY PIPELINED; HARDWARE ARCHITECTURE; HIGH-SPEED; HIT RATIO; IMAGE PAIRS; IMAGE PYRAMIDS; INPUT IMAGE; INTEGRATED CIRCUIT DESIGN; OPERATING FREQUENCY; PIPELINE DELAY; PROCESSING SPEED; REAL-TIME FACE DETECTION; RESOURCE UTILIZATIONS; SYNTHESIS TOOL;

COMPUTER VISION; DESIGN; FACE RECOGNITION; FORESTRY; PIPE;

FIELD PROGRAMMABLE GATE ARRAYS (FPGA);

FORESTRY; IMAGE ANALYSIS; PIPING;

EID: 84863037823     PISSN: 15513203     EISSN: None     Source Type: Journal    
DOI: 10.1109/TII.2011.2173943     Document Type: Article

References (20)

1. M.-H. Yang, D. J. Kriegman, and N. Ahuja, "Detecting faces in images: A survey," IEEE Trans. Pattern Anal. Mach. Intell., vol. 24, no. 1, pp. 34-58, Jan. 2002. (Pubitemid 34325615)
2. D. Zhang, S. Z. Li, and D. Gatica-Perez, "Real-time face detection using boosting in hierarchical feature spaces," in Proc. 17th Int. Conf. Pattern Recognit., Aug. 2004, pp. 411-414.
3. P. Viola and M. Jones, "Fast and robust classification using asymmetric AdaBoost and a detector cascade," Adv. Neural Inf. Process. Syst., vol. 2, pp. 1311-1318, 2002.
4. Y. Yan, Z. Guo, and J. Yang, "Multi-view face detection based on the enhanced AdaBoost using walsh features," in Proc. 8th ACIS Int. Conf. Softw. Eng., Artif. Intell., Netw., Parallel/Distrib. Comput., Jul. 2007, vol. 1, pp. 200-205. (Pubitemid 47533023)
5. B. Jun. and D. Kim, "Robust real-time face detection using face certainty map," in Lecture Notes Computer Science. Berlin, Germany: Springer, 2007, vol. 4642, pp. 29-38.
6. M. Grajcar, "Strengths and weaknesses of genetic list scheduling for heterogeneous systems," in Proc. 2nd Int. Conf. Appl. Concurr. Syst. Design, Jun. 2001, pp. 123-123.
7. Y. Wei, X. Bing, and C. Chareonsak, "FPGA implementation of AdaBoost algorithm for detection of face biometrics," in Proc. IEEE Int. Workshop Biomed. Circuits Syst., Dec. 2004, p. S1/6-17-20.
8. S. Asano, T. Maruyama, and Y. Yamaguchi, "Performance comparison of FPGA, GPU and CPU in image processing," in Proc. Int. Conf. Field Programmable Logic Appl., Aug. 2009, pp. 126-131.
9. B. Kisacanin, S. S. Bhattacharyya, and S. Chai, Embedded Computer Vision. New York: Springer, 2008.
10. H.-C. Lai, M. Savvides, and T. Chen, "Proposed FPGA hardware architecture for high frame rate (> 100 fps) face detection using feature cascade classifiers," in Proc. IEEE Int. Conf. Biometr.: Theory, Appl., Syst., Sep. 2007, pp. 1-6.
11. K. Irick, M. De Bole, V. Narayanan, R. Sharma, H. Moon, and S. Mummareddy, "A unified streaming architecture for real time face detection and gender classification," in Proc. Int. Conf. Field Programmable Logic Appl., Aug. 2007, pp. 267-272.
12. H. Ngo, R. Tompkins, J. Foytik, and V. Asari, "An area efficient modular architecture for real-time detection of multiple faces in video stream," in Proc. 6th Int. Conf. Inf., Commun. Signal Process., 2007, pp. 1-5.
13. N. Farrugia, F. Mamalet, S. Roux, F. Yang, and M. Paindvoine, "Fast and robust face detection on a parallel optimized architecture implemented on FPGA," IEEE Trans. Circuits Syst. Video Technol., vol. 19, no. 4, pp. 597-602, Apr. 2009.
14. M. Hiromoto, K. Nakahara, and H. Sugano, "A specialized processor suitable for AdaBoost-based detection with Haar-like features," in Proc. IEEE Conf. Comput. Vis. Pattern Recognit., Oct. 2007, pp. 1-8.
15. C. Gao and S. Lu, "Novel FPGA based Haar classifier face detection algorithm acceleration," in Proc. Int. Conf. Field Programm. Logic Appl., Sep. 2008, pp. 373-378.
16. J. Cho, S. Mirzaei, J. Oberg, and R. Kastner, "FPGA-based face detection system using Haar classifiers," in Proc. 17th ACM/SIGDA Int. Symp. Field-Programm. Gate Arrays, Dec. 2009, pp. 103-112.
17. C. He, A. Papakonstantinou, and D. Chen, "A novel SoC architecture on FPGA for ultra fast face detection," in Proc. IEEE Int. Conf. Comput. Design, Oct. 2009, pp. 412-418.
18. J. Diaz, E. Ros, F. Pelayo, E. M. Ortigosa, and S. Mota, "FPGA-based real-time optical-flow system," IEEE Trans. Circuits Syst. Video Technol., vol. 16, no. 2, pp. 274-279, Feb. 2006. (Pubitemid 43269787)
19. Xilinx XST User Guide 2008. [Online]. Available: http://www.xilinx.com
20. V. Jain and E. L. Miller, FDDB: A benchmark for face detection in unconstrained setting Dept. Comput. Sci., Univ. Massachusetts, Amherst, Tech. Rep. UM-CS-2010-009, 2010. [Online]. Available: http://vis-www.cs.umass.edu/fddb