Consequences of RAM bitline twisting for test coverage

Proceedings -Design, Automation and Test in Europe, DATE

Volumn , Issue , 2003, Pages 1176-1177

  Schanstra, Ivo ^a   Van De Goor, Ad J ^b  

^a INFINEON TECHNOLOGIES AG   (Germany)

^b DELFT UNIVERSITY OF TECHNOLOGY   (Netherlands)

Author keywords

[No Author keywords available]

Indexed keywords

BIT LINES; COUPLING EFFECT; DATA BACKGROUNDS; FAULT MODEL; TEST COVERAGE;

EXHIBITIONS; RANDOM ACCESS STORAGE;

DESIGN;

EID: 84893792430     PISSN: 15301591     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/DATE.2003.1253788     Document Type: Conference Paper

References (8)

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