An investigation into crosstalk noise in DRAM structures

Records of the IEEE International Workshop on Memory Technology, Design and Testing

Volumn 2002-January, Issue , 2002, Pages 123-129

  Redeker, M ^a   Cockburn, B F ^b   Elliott, D G ^b  

^a LEIBNIZ UNIVERSITY HANNOVER   (Germany)

^b UNIVERSITY OF ALBERTA   (Canada)

Author keywords

Capacitance; Circuit simulation; Coupling circuits; Crosstalk; Distributed parameter circuits; Integrated circuit interconnections; Maxwell equations; Predictive models; Random access memory; Solid modeling

Indexed keywords

CAPACITANCE; CIRCUIT SIMULATION; COUPLED CIRCUITS; CROSSTALK; INTEGRATED CIRCUIT INTERCONNECTS; MAXWELL EQUATIONS; RANDOM ACCESS STORAGE; WAVE PROPAGATION;

DISTRIBUTED PARAMETER CIRCUIT; INTEGRATED CIRCUIT INTERCONNECTIONS; PREDICTIVE MODELS; RANDOM ACCESS MEMORY; SOLID MODEL;

DYNAMIC RANDOM ACCESS STORAGE;

EID: 3142729804     PISSN: 10874852     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/MTDT.2002.1029773     Document Type: Conference Paper

References (15)

1. The International Technology Roadmap for Semiconductors 2001 (2001 ITRS Roadmap), Semiconductor Industry Association (SIA), 2001, http://public.itrs.net (Apr. 20, 2002).
2. H. B. Bakoglu, Circuits, Interconnects and Packaging for VLSI, Addison-Wesley, 1990.
3. A. Deutsch et al., "On-Chip Wiring Design Challenges for Gigahertz Operation," Proc. IEEE, vol. 89, no. 4, Apr. 2001, pp. 529-555.
4. R. L. M. Dang and N. Shigyo, "Coupling Capacitances for Two-Dimensional Wires," IEEE Electron Device Letters, vol. EDL-2, no. 8, Aug. 1981, pp. 196-197.
5. Y. Nakagome et al., "The Impact of Data-Line Interference Noise on DRAM Scaling," IEEE J. Solid-State Circuits, vol. 23, no. 5, Oct. 1988, pp. 1120-1127.
6. Z. Yang and S. Mourad, "Crosstalk in Deep Submicron DRAMs," Rec. IEEE Intl. Workshop on Memory Technology, Design and Testing, Aug. 7-8, 2000, pp. 125-129.
7. C.-G. Hwang, "Semiconductor Memories for IT Era," Dig. of Tech. Papers, ISSCC, Plenary session 1.2, Feb. 2002, pp. 22-27.
8. M. Yoshida, T. Takeshima, and M. Takada, "Scaled Bit Line Capacitance Analysis Using a Three-Dimensional Simulator," Symp. VLSI Technology, Dig. Tech. Papers, May 1985, pp. 66-67.
9. E. Grotelüschen et al., "LOSSYWIRE - A Model Implementation for Transient and AC Analysis of Lossy Coupled Transmission Lines in the Circuit Simulator ELDO," Intl. Journal of Electronics and Communications, vol. 49, no. 1, 1995, pp. 37-43.
10. P. Nordholz et al., "Signal Integrity Problems in Deep Submicron Arising from Interconnects between Cores," Proc. VLSI Test Symp., Apr. 26-30, 1998, pp. 28-33.
11. H. Grabinski, "An Algorithm for Computing the Signal Propagation on lossy VLSI Interconnect Systems in the Time Domain," VLSI Journal on Integration, vol. 7, no. 1, Apr. 1989, pp. 35-48.
12. K. Itoh, VLSI Memory Chip Design, Springer, 2001.
13. B. Davari et al., "CMOS Scaling for High Performance and Low Power - The Next Ten Years," Proc. IEEE, vol. 83, no. 4, Apr. 1995, pp. 595-606.
14. C. Werner et al., "Crosstalk Noise in Future Digital CMOS Circuits," Proc. DATE 2001, pp. 331-335.
15. B. Keeth and R. J. Baker, DRAM Circuit Design, IEEE Press, 2001.