Twisted bit-line technique for multi-gigabit DRAMs

Electronics Letters

Volumn 33, Issue 16, 1997, Pages 1380-1382

  Min, Dong Sun ^a   Langer, D W ^a  

^a University of Pittsburgh   (United States)

Author keywords

Random access storage; VLSI

Indexed keywords

BIT ERROR RATE; DATA REDUCTION; DATA TRANSFER; SIGNAL TO NOISE RATIO; VLSI CIRCUITS;

BIT LINE COUPLING NOISE;

RANDOM ACCESS STORAGE;

EID: 0031186477     PISSN: 00135194     EISSN: None     Source Type: Journal    
DOI: 10.1049/el:19970923     Document Type: Article

References (5)

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2. NITTA, Y., SAKASHITA, N., SHIMOMURA, K., OKUDA, F., SHIMANO, H., YAMAKAWA, S., FURUKAWA, A., and ABE, H.: 'A 1.6GB/S data-rate 1 Gb synchronous DRAM with hierarchical square-shaped memory block and distributed bank architecture'. ISSCC 96, Dig. Tech. Papers, February 1996, pp. 376-377
3. HIDAKA, H., FUJISHIMA, K., MATSUDA, Y., ASAKURA, M., and YOSHIHARA, T.: 'Twisted bit-line architectures for multi-megabit DRAMs', IEEE J. Solid-State Circuits, 1989, 24, (1), pp. 21-27
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5. TSUCHIDA, K., OOWAKI, Y., OHTA, M., TAKASHIMA, D., WATANABE, S., OHUCHI, K., and MASUOKA, F.: 'The stabilised reference-line technique for scaled DRAMs', IEEE J. Solid-State Circuits, 1990, 25, (1), pp. 24-29