Yield loss forecasting in the early phases of the VLSI design process

Proceedings of the Custom Integrated Circuits Conference

Volumn , Issue , 1996, Pages 27-30

  Heineken, Hans T ^a   Khare, Jitendra ^a   Maly, Wojciech ^a  

^a CARNEGIE MELLON UNIVERSITY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

FORECASTING; INTEGRATED CIRCUIT MANUFACTURE; MATHEMATICAL MODELS; TRANSISTORS; VLSI CIRCUITS; YIELD STRESS;

TRANSISTOR DENSITY; YIELD MEASUREMENT; YIELD MODELS;

INTEGRATED CIRCUIT LAYOUT;

EID: 0029703533     PISSN: 08865930     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (12)