Simulation of yield/cost learning curves with Y4

IEEE Transactions on Semiconductor Manufacturing

Volumn 10, Issue 2, 1997, Pages 256-266

  Nag, Pranab K ^a,b   Maly, Wojciech ^a,b   Jacobs, Hermann J ^a,c  

^a IEEE   (United States)

^b CARNEGIE MELLON UNIVERSITY   (United States)

^c SIEMENS AG   (Germany)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER SIMULATION; COST EFFECTIVENESS; FAILURE ANALYSIS; PROCESS CONTROL; SEMICONDUCTOR DEVICE TESTING; SILICON WAFERS;

DISCRETE EVENT SIMULATOR;

INTEGRATED CIRCUIT MANUFACTURE;

EID: 0031142594     PISSN: 08946507     EISSN: None     Source Type: Journal    
DOI: 10.1109/66.572080     Document Type: Article

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