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Volumn , Issue , 2003, Pages 504-509

Pre-characterization free, efficient power/performance analysis of embedded and general purpose software applications

Author keywords

[No Author keywords available]

Indexed keywords

ACCURATE ESTIMATION; CRITICAL SECTIONS; GENERAL PURPOSE PROCESSORS; GENERAL PURPOSE SOFTWARE; HYBRID SIMULATION; SAMPLING SCHEMES; SIMULATION SPEED-UP; TEMPORAL LOCALITY;

EID: 84893765176     PISSN: 15301591     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/DATE.2003.1253659     Document Type: Conference Paper
Times cited : (12)

References (16)
  • 2
    • 0033719421 scopus 로고    scopus 로고
    • Wattch: A framework for architectural-level power analysis and optimizations
    • Vancouver, BC, Canada June
    • D. Brooks, V. Tiwari and M. Martonosi, ?Wattch: A Framework for Architectural-Level Power Analysis and Optimizations,? in Proc. Intl. Symp. Computer Architecture, pp. 83-94, Vancouver, BC, Canada, June 2000.
    • (2000) Proc. Intl. Symp. Computer Architecture , pp. 83-94
    • Brooks, D.1    Tiwari, V.2    Martonosi, M.3
  • 4
    • 0033685446 scopus 로고    scopus 로고
    • An instructionlevel functionality-based energy estimation model for 32-bit microprocessors
    • June
    • C. Brandolese,W. Fornaciari, F. Salice and D. Sciuto, ?An instructionlevel functionality-based energy estimation model for 32-bit microprocessors,? in Proc. Design Automation Conf., pp. 346-351, June 2000.
    • (2000) Proc. Design Automation Conf. , pp. 346-351
    • Brandolese, C.1    Fornaciari, W.2    Salice, F.3    Sciuto, D.4
  • 5
    • 0032290914 scopus 로고    scopus 로고
    • Software power estimation and optimization for high-performance 32-bit embedded processors
    • October
    • J. Russell and M. Jacome, ?Software power estimation and optimization for high-performance 32-bit embedded processors,? in Proc. Int. Conf. Computer Design, pages 328-333, October 1998.
    • (1998) Proc. Int. Conf. Computer Design , pp. 328-333
    • Russell, J.1    Jacome, M.2
  • 7
    • 0028722375 scopus 로고
    • Power analyasis of embedded software: A first step towards software power minimization
    • December
    • V. Tiwari, S. Malik and A.Wolfe, ?Power analyasis of embedded software: A first step towards software power minimization,? in IEEE Tran. VLSI Systems, 2(4):437-445, December 1994.
    • (1994) IEEE Tran. VLSI Systems , vol.2 , Issue.4 , pp. 437-445
    • Tiwari, V.1    Malik, S.2    Wolfe, A.3
  • 9
    • 84893689640 scopus 로고    scopus 로고
    • Efficient power co-estimation techniques for system-on-chip design
    • March
    • M. Lajolo, A. Raghunathan and S. Dey, ?Efficient Power Co-Estimation Techniques for System-on-Chip Design,? in Proc. Design & Test Europe, pp.27-34, March 2000.
    • (2000) Proc. Design & Test Europe , pp. 27-34
    • Lajolo, M.1    Raghunathan, A.2    Dey, S.3
  • 13
    • 0032629113 scopus 로고    scopus 로고
    • A hardware-driven profiling scheme for identifying program hot spots to support runtime optimization
    • May
    • Matthew C. Merten, Andrew R. Trick, Christopher N. George, John C. Gyllenhaal, and Wen-mei W. Hwu ?A Hardware-Driven Profiling Scheme for Identifying Program Hot Spots to Support Runtime Optimization,? in Proc. Int. Symp. Computer Architecture, pp. 136-147, May, 1999.
    • (1999) Proc. Int. Symp. Computer Architecture , pp. 136-147
    • Matthew, C.M.1    Trick, A.R.2    George, C.N.3    Gyllenhaal, J.C.4    Hwu, W.W.5
  • 16
    • 0035212915 scopus 로고    scopus 로고
    • Application-driven processor design exploration for power-performance trade-off analysis
    • San Jose, USA, Nov.
    • D. Marculescu and A. Iyer, ?Application-Driven Processor Design Exploration for Power-Performance Trade-off Analysis,? in Proc. IEEE/ACM Intl. Conf. on Computer-Aided Design, San Jose, USA, Nov. 2001.
    • (2001) Proc. IEEE/ACM Intl. Conf. on Computer-Aided Design
    • Marculescu, D.1    Iyer, A.2


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.