Dual threshold voltage domino logic synthesis for high performance with noise and power constraint

Proceedings -Design, Automation and Test in Europe, DATE

Volumn , Issue , 2002, Pages 260-265

  Jung, Seong Ook ^a   Kim, Ki Wook ^b   Kang, Sung Mo ^c  

^a University of Illinois at Urbana Champaign   (United States)

^b Pluris Inc   (United States)

^c University of California Santa Cruz   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ACTIVE POWER; DOMINO LOGIC; DUAL THRESHOLD VOLTAGE; NOISE MARGINS; OPTIMAL DESIGN; POWER CONSTRAINTS; SIGNAL INTEGRITY; TRANSISTOR SIZING;

EXHIBITIONS; THRESHOLD VOLTAGE;

BENCHMARKING;

EID: 84893758505     PISSN: 15301591     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/DATE.2002.998282     Document Type: Conference Paper

References (8)

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