Fault model for VHDL descriptions at the register transfer level

European Design Automation Conference - Proceedings

Volumn , Issue , 1996, Pages 462-467

  Riesgo, T ^a   Uceda, J ^a  

^a UNIVERSIDAD POLITÉCNICA DE MADRID   (Spain)

Author keywords

[No Author keywords available]

Indexed keywords

ELECTRIC NETWORK SYNTHESIS; FAILURE ANALYSIS; INTEGRATED CIRCUIT LAYOUT; INTEGRATED CIRCUIT TESTING; MATHEMATICAL MODELS; SHIFT REGISTERS;

FAULT COVERAGE; FAULT MODEL; LOGIC LEVEL FAULT MODEL; REGISTER TRANSFER LEVEL;

COMPUTER HARDWARE DESCRIPTION LANGUAGES;

EID: 0029746899     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (9)