A power-gated MPU with 3-microsecond entry/exit delay using MTJ-based nonvolatile flip-flop

Proceedings of the 2013 IEEE Asian Solid-State Circuits Conference, A-SSCC 2013

Volumn , Issue , 2013, Pages 317-320

  Koike, H ^a   Ohsawa, T ^a   Ikeda, S ^a   Hanyu, T ^a   Ohno, H ^a   Endoh, T ^a   Sakimura, N ^a,b   Nebashi, R ^b   Tsuji, Y ^b   Morioka, A ^b   Miura, S ^b   Honjo, H ^b   Sugibayashi, T ^b  

^a TOHOKU UNIVERSITY   (Japan)

^b NEC CORPORATION   (Japan)

Author keywords

Flip flop; MPU; MTJ; Nonvolatile; Power gating

Indexed keywords

FLIP-FLOP; MPU; MTJ; NON-VOLATILE; POWER GATINGS;

FLIP FLOP CIRCUITS;

MAGNETIC DEVICES;

EID: 84893578823     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ASSCC.2013.6691046     Document Type: Conference Paper

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