A 6 bit 2 GS/s flash-assisted time-interleaved (FATI) SAR ADC with background offset calibration

Proceedings of the 2013 IEEE Asian Solid-State Circuits Conference, A-SSCC 2013

Volumn , Issue , 2013, Pages 281-284

  Sung, Ba Ro Saim ^a   Lee, Chang Kyo ^a   Kim, Wan ^a   Kim, Jong In ^a   Hong, Hyeok Ki ^a   Oh, Ghil Geun ^a   Lee, Choong Hoon ^b   Choi, Michael ^b   Park, Ho Jin ^b   Ryu, Seung Tak ^a  

^a Korea Advanced Institute of Science and Technology (KAIST)   (South Korea)

^b SAMSUNG Electronics   (South Korea)

Author keywords

[No Author keywords available]

Indexed keywords

45 NM CMOS; FLASH-ADC; LOW RESOLUTION; OFFSET CALIBRATION; POWER EFFICIENT; SAR ADC; TIME-INTERLEAVED; TIME-INTERLEAVING;

CALIBRATION; ENERGY UTILIZATION;

ANALOG TO DIGITAL CONVERSION;

EID: 84893532326     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ASSCC.2013.6691037     Document Type: Conference Paper

References (9)

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2. Simon M. Louwsma, et al., "A 1.35 GS/s, 10b, 175 mW time-interleaved AD converter in 0.13 μm CMOS," in Symp. VLSI Circuits Dig. Tech. Papers, Jun. 2007, pp. 62-63.
3. Ba-Ro-Saim Sung, et Al., "A time-interleaved flash-SAR architecture for high speed A/D conversion," in IEEE ISCAS, No. 2, pp. 984-987, May. 2009.
4. Masashi Kijima, et Al., "A 6b 3GS/s Flash ADC with Background Calibration," in Proc. IEEE CICC, Sept 2009, pp. 283-286.
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6. V. Hariprasath, et Al., "Merged capacitor switching based SAR ADC with highest switching energy-efficiency"in IEEE Electronics Letters, Apr. 2010, pp. 620-621.
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8. Zhiheg Cao, Shouli Yan, Yunchu Li, "A 32mW 1.25GS/s 6b 2b/step SAR ADC in 0.13μm CMOS," in IEEE Conf. ISSCC Dig. Tech. papers, pp. 542-543, Feb. 2008.
9. Manar El-Chammas, Boris Murmann, "A 12-GS/s 81-mW 5-bit Time-Interleaved Flash ADC With Background Timing Skew Calibration," in IEEE JSSC, pp. 834-847, Apr. 2011.