Queue machines: Hardware compilation in hardware

IEEE Symposium on FPGAs for Custom Computing Machines, Proceedings

Volumn 2002-January, Issue , 2002, Pages 152-162

  Schmit, Herman ^a   Levine, Benjamin ^a   Ylvisaker, Benjamin ^a  

^a CARNEGIE MELLON UNIVERSITY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER ARCHITECTURE; COMPUTERS; COUPLINGS; HARDWARE; QUEUEING THEORY; RECONFIGURABLE ARCHITECTURES; RECONFIGURABLE HARDWARE;

COMPUTING MACHINES; HARDWARE COMPILATION; HARDWARE VIRTUALIZATION; INSTRUCTION SET ARCHITECTURE; RE-CONFIGURABLE COMPUTING APPLICATIONS; RECONFIGURABLE COMPUTING; RECONFIGURABLE FABRICS; SPATIAL REPRESENTATIONS;

COMPUTER HARDWARE;

EID: 84888862616     PISSN: 10823409     EISSN: None     Source Type: Journal    
DOI: 10.1109/FPGA.2002.1106670     Document Type: Article

References (14)

1. S. C. Goldstein, H. Schmit, M. Budiu, S. Cadambi, M. Moe, R. R. Taylor, "PipeRench: A Reconfigurable Architecture and Compiler" in Computer, pp. 70-77, April, 2000.
2. D. Cronquist, P. Franklin, S. Berg, and C. Ebeling, "Specifying and Compiling Applications for RaPiD", in Proc. IEEE Workshop on FPGAs for Custom Computing Machines, (FCCM), pp. 116-127, 1998.
3. L. S. Heath, S. V. Pemmaraju, A. N. Trenk, "Stack and Queue Layouts of Directed Acyclic Graphs: Part I", SIAM J. Comput. Vol 23, No. 4, pp. 1510-1539.
4. PACT Corporation, "Parallel and Sequential XPP Processing Models", http://w w w.pactcorp. com/.
5. M. Jünger, S. Leipert, and P. Mutzel, "Level Planarity Testing in Linear Time", Technical Report, Zentrum für Angewandte Informatik Köln, Lehrstuhl Jünger, URL: http://www.zaik.uni-koeln. de/paper, 1999.
6. B. R. Preiss and V. C. Hamacher. "Data Flow on a Queue Machine", in Proc. 12th Int. Symp. on Computer Architecture, pages 342-351, Boston, MA, August 1985.
7. S. Okamoto, "Design of a Superscalar Processor Based on Queue Machine Computation Model", IEEE Pacific Rim Conference on Communications, Computers and Signal Processing, pp. 151-154, 1999.
8. W. A. Wulf, "Evaluation of the WM Architecture", Proc. 19th Int. Symp. on Computer Architecture, pages 382-390, 1992.
9. T. Lindholm and F. Yellin, The Java Virtual Machine Specification, Second Edition, Addison-Wesley, 1999.
10. T. R. Halfhill, "Transmeta Breaks x86 Low-Power Barrier", in Microprocessor Report, Vol. 14, Archive 2, pp. 1, 9-18, Feb. 2000.
11. L. Gwennap, "Intel's P6 Uses Decoupled Superscalar Design", Microprocessor Report, Vol. 9, Issue 2, Feb. 1995.
12. M. M. Fernandes, J. Llosa, and N. Topham, Using Queues for Register File Organization in VLIW Architectures, Technical Report ECS-CSG 29-97, Dept of Computer Science, University of Edinburgh, 1997.
13. E. Rotenberg, S. Bennett, and J. E. Smith, "Trace Cache: A Low Latency Approach to High Bandwidth Instruction Fetching", in Proc. of the 29th Annual Intl Symp. on Microarchitecture, November 1996.
14. S. Vajapeyam, P. J. Joseph, T. Mitra, "Dynamic Vectorization: A Mechanism for Exploiting Far-Flung ILP in Ordinary Programs", in International Symposium on Computer Architecture, pp. 16-27, 1999.