Assessment of true worst case circuit performance under interconnect parameter variations

Proceedings - International Symposium on Quality Electronic Design, ISQED

Volumn 2001-January, Issue , 2001, Pages 431-436

  Acar, Emrah ^a   Nassif, Sani ^b   Liu, Ying ^b   Pileggi, Lawrence T ^a  

^a CARNEGIE MELLON UNIVERSITY   (United States)

^b IBM AUSTIN RESEARCH LABORATORY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ITERATIVE METHODS;

ANALYTICAL APPROXIMATION; CIRCUIT PERFORMANCE; INTERCONNECT PARAMETER; ITERATIVE SEARCH TECHNIQUES; MANUFACTURING PROCESS; PERFORMANCE METRICS; PROCESS VARIATION; TIMING PERFORMANCE;

INTEGRATED CIRCUIT INTERCONNECTS;

EID: 84949955220     PISSN: 19483287     EISSN: 19483295     Source Type: Conference Proceeding    
DOI: 10.1109/ISQED.2001.915267     Document Type: Conference Paper

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