Customizable embedded processor architectures

Proceedings - Euromicro Symposium on Digital System Design, DSD 2003

Volumn , Issue , 2003, Pages 468-475

  Petrov, P ^a   Orailoglu, A ^a  

^a UNIVERSITY OF CALIFORNIA   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER AIDED DESIGN; SYSTEMS ANALYSIS;

APPLICATION PROPERTIES; ARCHITECTURAL PRINCIPLES; DYNAMIC APPLICATIONS; EMBEDDED PROCESSOR ARCHITECTURE; EMBEDDED PROCESSORS; MICRO ARCHITECTURES; PROPOSED ARCHITECTURES; REPROGRAMMABLE HARDWARE;

MEMORY ARCHITECTURE;

CAD CAM; DATA STORAGE; ELECTRIC CIRCUITS;

EID: 84885609500     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/DSD.2003.1231986     Document Type: Conference Paper

References (10)

1. P. Petrov and A. Orailoglu, "Performance and power effectiveness in embedded processors - Customizable Partitioned Caches", IEEE TCAD, vol. 20, n. 11, pp. 1309-1318, November 2001.
2. P. Petrov and A. Orailoglu, "Power Efficient Embedded Processor IP's through Application-Specific Tag Compression in Data Caches", in DATE, pp. 1065-1071, March 2002.
3. P. Petrov and A. Orailoglu, "Low-power Data Memory Communication for Application-Specific Embedded Processors", in ISSS, pp. 219-224, October 2002.
4. M. E. Wolf and M. S. Lam, "A Data Locality Optimizing Algorithm", in PLDI, pp. 30-44, June 1991.
5. J. Montanaro et al., "A 160Mhz, 32b 0.5W CMOS RISC Microprocessor", in IEEE ISCC, pp. 214-229, February 1996.
6. E. Witchel and K. Asanovic, "The span cache: software controlled tag checks and cache line size", in Workshop on Complexity-Effective Design, 28th ISCA, June 2001.
7. K. Inoue, T. Ishihara and K. Murakami, "Way-predicting set-associative cache for high-performance and low energy consumption", in ISLPED, pp. 273-275, August 1999.
8. C. Lee, M. Potkonjak and W. H. Mangione-Smith, "Media-Bench: A Tool for Evaluating and Synthesizing Multimedia and Communications Systems", in 30th MICRO, pp. 330-335, December 1997.
9. P. Petrov and A. Orailoglu, "Data Cache Energy Minimization through Programmable Tag Size Matching to the Application", in ISSS, pp. 113-117, September 2001.
10. M. S. Lam, E. E. Rothberg and M. E. Wolf, "The Cache Performance and Optimizations of Blocked Algorithms", in 4th ASP-LOS, pp. 63-74, April 1991.