Real-time interface board for closed-loop robotic tasks on the SpiNNaker neural computing system

Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)

Volumn 8131 LNCS, Issue , 2013, Pages 467-474

  Denk, Christian ^a   Llobet Blandino, Francisco ^a   Galluppi, Francesco ^b   Plana, Luis A ^b   Furber, Steve ^b   Conradt, Jörg ^a  

^a TECHNICAL UNIVERSITY OF MUNICH   (Germany)

^b UNIVERSITY OF MANCHESTER   (United Kingdom)

Author keywords

hardware interface board; massively parallel simulation of spiking neurons; mobile robotics; SpiNNaker

Indexed keywords

ASYNCHRONOUS INTERFACE; HARDWARE INTERFACES; HIGH COMPUTATION SPEED; INTERNAL COMMUNICATIONS; MOBILE ROBOTIC; REAL TIME INTERFACES; SPIKING NEURON; SPINNAKER;

COMPUTER SIMULATION; ELECTROPHYSIOLOGY; HARDWARE; LOW POWER ELECTRONICS; NETWORKS (CIRCUITS); ROBOTICS;

NEURAL NETWORKS;

EID: 84884929914     PISSN: 03029743     EISSN: 16113349     Source Type: Book Series    
DOI: 10.1007/978-3-642-40728-4_59     Document Type: Conference Paper

References (10)

1. Pfeil, T., Grübl, A., Jeltsch, S., Müller, E., Müller, P., Petrovici, M.A., Schmuker, M., Brüderle, D., Schemmel, J., Meier, K.: Six Networks on a Universal Neuromorphic Computing Substrate. Frontiers in Neuroscience 7 (2013)
2. Choudhary, S., Sloan, S., Fok, S., Neckar, A., Trautmann, E., Gao, P., Stewart, T., Eliasmith, C., Boahen, K.: Silicon Neurons That Compute. In: Villa, A.E.P., Duch, W., Érdi, P., Masulli, F., Palm, G. (eds.) ICANN 2012, Part I. LNCS, vol. 7552, pp. 121-128. Springer, Heidelberg (2012)
3. Badoni, D., Giulioni, M., Dante, V., Del Giudice, P.: An Avlsi Recurrent Network of Spiking Neurons with Reconfigurable and Plastic Synapses. In: IEEE (ISCAS), pp. 1227-1230 (2006)
4. Khan, M., Lester, D., Plana, L.A., Rast, A., Jin, X., Painkras, E., Furber, S.B.: SpiNNaker: Mapping Neural Networks onto a Massively-Parallel Chip Multiprocessor. In: IEEE International Joint Conference on Neural Networks (IJCNN), pp. 2849-2856. IEEE (2008)
5. Plana, L.A., Bainbridge, J., Furber, S., Salisbury, S., Shi, Y., Wu, J.: An on-Chip and Inter-Chip Communications Network for the SpiNNaker Massively-Parallel Neural Net Simulator. In: 2nd ACM/IEEE NoCS, pp. 215-216. IEEE (2008)
6. Galluppi, F., Davies, S., Rast, A., Sharp, T., Plana, L.A., Furber, S.: A Hierachical Configuration System for a Massively Parallel Neural Hardware Platform. In: Proceedings of the 9th conference on Computing Frontiers, pp. 183-192. ACM (2012)
7. Galluppi, F., Davies, S., Furber, S., Stewart, T., Eliasmith, C.: Real Time on-Chip Implementation of Dynamical Systems with Spiking Neurons. In: IJCNN, pp. 1-8. IEEE (2012)
8. Oster, M., Douglas, R., Liu, S.-C.: Computation with Spikes in a Winner-Take-All Network. Neural Computation 21, 2437-2465 (2009)
9. Lichtsteiner, P., Posch, C., Delbruck, T.: A 128 128 120dB 15ms Latency Asynchronous Temporal Contrast Vision Sensor. IEEE Solid-State Circuits 43, 566-576 (2008)
10. Conradt, J., Berner, R., Cook, M., Delbruck, T.: An Embedded AER Dynamic Vision Sensor for Low-Latency Pole Balancing. In: IEEE ECV, pp. 780-785. IEEE (2009)