An on-chip and inter-chip communications network for the SpiNNaker Massively-Parallel Neural Net Simulator

Proceedings - Second IEEE International Symposium on Networks-on-Chip, NOCS 2008

Volumn , Issue , 2008, Pages 215-216

  Plana, Luis A ^a   Bainbridge, John ^b   Furber, Steve ^a   Salisbury, Sean ^b   Shi, Yebin ^a   Wu, Jian ^a  

^a UNIVERSITY OF MANCHESTER   (United Kingdom)

^b Silistix Ltd

Author keywords

[No Author keywords available]

Indexed keywords

EID: 44149121001     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/NOCS.2008.4492744     Document Type: Conference Paper

References (2)

1. L.A. Plana, S.B. Furber, S. Temple, M. Khan, Y. Shi, J. Wu, and S. Yang. A GALS Infrastructure for a Massively Parallel Multiprocessor. IEEE Design & Test of Computers, 24(5):454-463, Sept.-Oct. 2007.
2. John Bainbridge and Steve Furber. CHAIN: A Delay-Insensitive Chip Area Interconnect. IEEE Micro, 22(5): 16-23, Sept.-Oct. 2002.