An 8.5 mW, 0.07 mm2 ADPLL in 28 nm CMOS with sub-ps resolution TDC and < 230 fs RMS jitter

IEEE Symposium on VLSI Circuits, Digest of Technical Papers

Volumn , Issue , 2013, Pages

  Shen, Bo ^a   Unruh, Greg ^a   Lugthart, Marcel ^a   Lee, Chang Hyeon ^a   Chambers, Mark ^a  

^a BROADCOM CORPORATION   (United States)

Author keywords

ADPLL; limit cycle; quantization noise; TDC

Indexed keywords

ADPLL; ALL-DIGITAL PLL; HIGH RESOLUTION; LIMIT-CYCLE; QUANTIZATION NOISE; REFERENCE FREQUENCY; TDC; TIME TO DIGITAL CONVERTERS;

FREQUENCY CONVERTERS; VLSI CIRCUITS;

JITTER;

EID: 84883785955     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (6)

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