Power comparison of 2D, 3D and 2.5D interconnect solutions and power optimization of interposer interconnects

Proceedings - Electronic Components and Technology Conference

Volumn , Issue , 2013, Pages 860-866

  Karim, M Ataul ^a   Franzon, Paul D ^a   Kumar, Anil ^b  

^a NORTH CAROLINA STATE UNIVERSITY   (United States)

^b SEMATECH   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

32 NM TECHNOLOGY; 3D INTERCONNECT; BACK END OF THE LINES; POWER COMPARISON; POWER EFFICIENCY; POWER OPTIMIZATION; THROUGH SILICON VIAS; TRACE LENGTH;

ELECTRONICS PACKAGING; OPTIMIZATION; ORGANIC POLLUTANTS; POLYCHLORINATED BIPHENYLS; THREE DIMENSIONAL;

EFFICIENCY;

EID: 84883442943     PISSN: 05695503     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ECTC.2013.6575674     Document Type: Conference Paper

References (7)

1. IBIS model, 2GB DDR3-1066; http://www.elpida.com/en/products/ddr3.html
2. D. B. Lin, M. P. Houng and W. S. Liu, "Enhancement of Signal Integrity for Multi-Module Memory Bus by Particle Swarm Optimization," in Proc. IEEE 11th annual, Wireless and Microwave Technology Conference (WAMICON) 2010, pp. 1-5
3. J. Sjoberg, S. Alam, D. A. Geiger and D. Shangguan, "Process Development and Reliability Evaluation for Inline Package-on-Package (PoP) Assembly," in Proc. Electronic Components and Technology Conference, 2008, pp. 2005-2010
4. W. Yuan, C. K. Wang, Z. Boyu, N. Suthiwongsunthorn, S. Chungpaiboonpatana, "Electrical Performance Evaluation & Comparison of High-Speed Multiple-Chip 3D Packages" in Proc. 12th Electronics Packaging Technology Conference, 2010, pp. 114-119
5. S. R. Vempati, N. Su, C. H. Khong, Y. Y. Lim, K. Vaidyanathan, J. H. Lau,B. P. Liew, K. Y. Au, S. Tanary, A. Fenner, R. Erich, J. Milla, "Development of 3-D Silicon Die Stacked Package Using Flip Chip Technology with Microbump Interconnects," in Proc. IEEE Electronic Components and Technol. Conf. May 26-29, 2009, pp. 980-987
6. Q. Cui, X. Sun, Y. Zhu, S. Ma, J. Chen, M. Miao, Y. Jin, "Design and optimixation of Redistribution Layer (RDL) on TSV interposer for high frequency application," in Proc. IEEE International conference on Electrical Packaging Technilogy & High Density Packaging, August 8-11, 2011, pp. 1-5
7. http://ptm.asu.edu/modelcard/LP/32nm-LP.pm