3D stacking for multi-core architectures: From WIDEIO to distributed caches

Proceedings - IEEE International Symposium on Circuits and Systems

Volumn , Issue , 2013, Pages 537-540

  Clermidy, F ^a   Dutoit, D ^a   Guthmuller, E ^a   Miro Panades, I ^a   Vivet, P ^a  

^a CEA LETI   (France)

Author keywords

[No Author keywords available]

Indexed keywords

DISTRIBUTED CACHE; EXTERNAL MEMORY; MEMORY LATENCIES; MEMORY PARTITIONING; MULTICORE ARCHITECTURES; NETWORK ON CHIP; PERFORMANCE BASED; THROUGH SILICON VIAS;

CACHE MEMORY; DYNAMIC RANDOM ACCESS STORAGE; SERVERS; THREE DIMENSIONAL; VLSI CIRCUITS;

COMPUTER ARCHITECTURE;

EID: 84883330334     PISSN: 02714310     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ISCAS.2013.6571899     Document Type: Conference Paper

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