Precise micro-architectural modeling for WCET analysis via AI+SAT

Real-Time Technology and Applications - Proceedings

Volumn , Issue , 2013, Pages 87-96

  Banerjee, Abhijeet ^a   Chattopadhyay, Sudipta ^a   Roychoudhury, Abhik ^a  

^a NATIONAL UNIVERSITY OF SINGAPORE   (Singapore)

Author keywords

[No Author keywords available]

Indexed keywords

ABSTRACT INTERPRETATIONS; BRANCH PREDICTORS; HARD REAL-TIME SYSTEMS; INSTRUCTION CACHES; PERFORMANCE ENHANCING; RESEARCH ADVANCES; SCHEDULABILITY ANALYSIS; WORST-CASE EXECUTION TIME;

CACHE MEMORY; EMBEDDED SYSTEMS; REGRESSION ANALYSIS;

REAL TIME SYSTEMS;

EID: 84881093976     PISSN: 10801812     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/RTAS.2013.6531082     Document Type: Conference Paper

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