Intrinsic dielectric stack reliability of a high performance bulk planar 20nm replacement gate high-k metal gate technology and comparison to 28nm gate first high-k metal gate process

IEEE International Reliability Physics Symposium Proceedings

Volumn , Issue , 2013, Pages

  McMahon, W ^a   Tian, C ^a   Uppal, S ^b   Kothari, H ^a   Jin, M ^b   Larosa, G ^a   Nigam, T ^a   Kerber, A ^a   Linder, B P ^c   Cartier, E ^c   Lai, W L ^a   Liu, Y ^a   Ramachandran, R ^a   Kwon, U ^a   Parameshwaran, B ^a   Krishnan, S ^a   Narayanan, V ^c  

^a IBM MICROELECTRONICS   (United States)

^b SAMSUNG Electronics   (South Korea)

^c IBM T J WATSON RESEARCH CENTER   (United States)

Author keywords

high k gate dielectrics; semiconductor device reliability

Indexed keywords

DIELECTRIC STACK; GATE FIRST; GATE TECHNOLOGY; HIGH-K GATE DIELECTRICS; HIGH-K METAL GATES; SEMICONDUCTOR DEVICE RELIABILITY; SILICON GERMANIUM; TECHNOLOGY IMPACT;

RELIABILITY; TECHNOLOGY;

INTEGRATED CIRCUITS;

EID: 84881016602     PISSN: 15417026     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/IRPS.2013.6532016     Document Type: Conference Paper

References (10)

1. X. Chen, et al, "A cost effective 32nm high-K/ metal gate CMOS technology for low power applications with single-metal/gate-first process," VLSI Technology. pp. 88-89, 2008.
2. F. Arnaud et al., "32nm general purpose bulk CMOS technology for high performance applications at low voltage," pp. 1-4, IEDM 2008.
3. F. Arnaud et al., "Competitive and cost effective high-k based 28nm CMOS technology for low power applications," pp. 1-4, IEDM 2009.
4. C. Auth et al., "A 22nm high performance and low-power CMOS technology featuring fully-depleted tri-gate transistors, self-aligned contacts and high density MIM capacitors," pp. 131-132, VLSI 2012.
5. 2," pp. 230-231, VLSI 2005.
6. S. Krishnan et al., "A manufacturable dual channel (Si and SiGe) high-k metal gate CMOS technology with multiple oxides for high performance and low power applications," pp. 28.1.1-28.1.4, IEDM 2011.
7. A. Kerber, S. A. Krishnan, E. A. Cartier, "Voltage Ramp Stress for Bias Temperature Instability Testing of Metal-Gate/High-k Stacks," IEEE EDL, pp. 1347-1349, 2009.
8. E. Cartier et al., "Fundamental aspects of HfO2-based high-k metal gate stack reliability and implications on tinv-scaling," IEDM pp. 18.4.1-18.4.4, 2011.
9. A. Kerber et al., "Reliability Challenges for CMOS Technology Qualifications With Hafnium Oxide/Titanium Nitride Gate Stacks," IEEE Trans. Dev. Mat. Reliability, Vol. 9, pp. 147-162, 2009.
10. J. Franco et al., "Superior NBTI reliability of SiGe channel pMOSFETs: Replacement gate, Fin FETs, and impact of Body Bias," IEDM pp. 18.5.1-18.5.4, 2011.