Application of VRS methodology for the statistical assessment of BTI in MG/HK CMOS devices

IEEE Electron Device Letters

Volumn 34, Issue 8, 2013, Pages 960-962

  Kerber, Andreas ^a   Cartier, Eduard ^b  

^a IBM MICROELECTRONICS   (United States)

^b IBM T J WATSON RESEARCH CENTER   (United States)

Author keywords

Bias temperature instability; CMOS devices; high k dielectrics; metal gate; variability; voltage ramp stress (VRS)

Indexed keywords

BIAS TEMPERATURE INSTABILITY; CMOS DEVICES; HIGH-K DIELECTRIC; METAL GATE; VARIABILITY; VOLTAGE RAMP;

CMOS INTEGRATED CIRCUITS; GATE DIELECTRICS; STOCHASTIC SYSTEMS;

INTEGRATED CIRCUITS;

EID: 84881002353     PISSN: 07413106     EISSN: None     Source Type: Journal    
DOI: 10.1109/LED.2013.2268050     Document Type: Article

References (9)

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