Aggressive SiGe channel gate stack scaling by remote Oxygen scavenging: Gate-first pFET performance and reliability

ECS Solid State Letters

Volumn 2, Issue 2, 2013, Pages

  Frank, Martin M ^a   Cartier, Eduard A ^a   Ando, Takashi ^a   Bedell, Stephen W ^a   Bruley, John ^a   Zhu, Yu ^a   Narayanan, Vijay ^a  

^a IBM T J WATSON RESEARCH CENTER   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

EQUIVALENT OXIDE THICKNESS; GATE DIELECTRIC SCALING; HIGH-K/METAL GATES; INTERLAYER THICKNESS; METAL-OXIDE-SEMICONDUCTOR FIELD-EFFECT TRANSISTOR; NEGATIVE BIAS TEMPERATURE INSTABILITY; PERFORMANCE AND RELIABILITIES; STRAINED SILICON-GERMANIUM CHANNEL;

GATE DIELECTRICS; MOSFET DEVICES; SCAVENGING;

INTEGRATED CIRCUITS;

EID: 84880521455     PISSN: 21628742     EISSN: 21628750     Source Type: Journal    
DOI: 10.1149/2.005302ssl     Document Type: Article

References (19)

1. S. Krishnan, U. Kwon, N. Moumen, M. W. Stoker, E. C. T. Harley, S. Bedell, D. Nair, B. Greene, W. Henson, M. Chowdhury, D. P. Prakash, E. Wu, D. Ioannou, E. Cartier, M.-H. Na, S. Inumiya, K. Mcstay, L. Edge, R. Iijima, J. Cai, M. Frank, M. Hargrove, A. Kerber, H. Jagannathan, T. Ando, J. Shepard, S. Siddiqui, M. Dai, H. Bu, J. Schaeffer, D. Jaeger, K. Barla, T. Wallner, S. Uchimura, Y. Lee, G. Karve, S. Zafar, D. Schepis, Y. Wang, R. Donaton, S. Saroop, P. Montanini, Y. Liang, J. Stathis, R. Carter, R. Pal, V. Paruchuri, H. Yamasaki, J-H. Lee, M. Ostermayr, J-P. Han, Y. Hu, M. Gribelyuk, D.-G. Park, X. Chen, S. Samavedam, S. Narasimha, P. Agnello, M. Khare, R. Divakaruni, V. Narayanan, and M. Chudzik, IEDM Tech. Dig. (2011), p. 634.
2. J. Franco, B. Kaczer, G. Eneman, J. Mitard, A. Stesmans, V. Afanas'ev, T. Kauerauf, Ph. J. Roussel, M. Toledano-Luque, M. Cho, R. Degraeve, T. Grasser, L.-Å. Ragnarsson, L. Witters, J. Tseng, S. Takeoka, W.-E. Wang, T. Y. Hoffmann, and G. Groeseneken, IEDM Tech. Dig. (2010), p. 70.
3. L. Witters, S. Takeoka, S. Yamaguchi, A. Hikavyy, D. Shamiryan, M. Cho, T. Chiarella, L.-Å. Ragnarsson, R. Loo, C. Kerner, Y. Crabbe, J. Franco, J. Tseng, W. E. Wang, E. Rohr, T. Schram, O. Richard, H. Bender, S. Biesemans, P. Absil, and T. Hoffmann, VLSI Tech. Dig. (2010), p. 181.
4. L. Witters, IEDM Tech. Dig. (2011), p. 654.
5. D. C. Gilmer, J. K. Schaeffer, W. J. Taylor, C. Capasso, K. Junker, J. Hildreth, D. Tekleab, B. Winstead, and S. B. Samavedam, IEEE Trans. Electron Devices, 57, 898 (2010).
6. T. Ando, M. M. Frank, K. Choi, C. Choi, J. Bruley, M. Hopstaken, M. Copel, E. Cartier, A. Kerber, A. Callegari, D. Lacey, S. Brown, Q. Yang, and V. Narayanan, IEDM Tech. Dig. (2009), p. 423.
7. T. Ando, M. Copel, J. Bruley, M. M. Frank, H. Watanabe, and V. Narayanan, Appl. Phys. Lett., 96, 132904 (2010).
8. T. Ando, Materials, 5, 478 (2012).
9. J. Franco, B. Kaczer, M. Cho, G. Eneman, G. Groeseneken, and T. Grasser, Proc. IRPS (2010), p. 1082.
10. H. Jagannathan, K. Watanabe, H. Sunamura, K. Ariyoshi, S. Allegret-Maret, and V. K. Paruchuri, as discussed at the 2011 IEEE SISC, Arlington, VA.
11. S. Subbanna, V. P. Kesan, M. J. Tejwani, P. J. Restle, D. J. Mis, and S. S. Iyer, VLSI Tech. Dig. (1991), p. 103.
12. P. M. Garone, V. Venkataraman, and J. C. Sturm, IEDM Tech. Dig. (2001), p. 29.
13. M. M. Frank, Proc. of the 41st European Solid-State Device Research Conf. (ESSDERC) (2011), p. 25.
14. J. R. Hauser and K. Ahmed, AIP Conf. Proc., 449, 235 (1998).
15. M. Fischetti, D. Neumayer, and E. Cartier, J. Appl. Phys., 90, 4587 (2001).
16. T. Yamaguchi, R. Iijima, T. Ino, A. Nishiyama, H. Satake, and N. Fukushima, IEDM Tech. Dig. (2002), p. 621.
17. M. Goto, S. Kawanaka, S. Inumiya, N. Kusunoki, M. Saitoh, K. Tatsumura, A. Kinoshita, S. Inaba, and Y. Toyoshima, VLSI Tech. Dig. (2009), p. 214.
18. E. Cartier, A. Kerber, T. Ando, M. M. Frank, K. Choi, S. Krishnan, B. Linder, K. Zhao, F. Monsieur, J. Stathis, and V. Narayanan, IEDM Tech. Dig. (2011), p. 441.
19. T. Grasser and B. Kaczer, IEEE Trans. Electron Devices, 56, 1056 (2009).