Improving multi-core performance using mixed-cell cache architecture

Proceedings - International Symposium on High-Performance Computer Architecture

Volumn , Issue , 2013, Pages 119-130

  Khan, Samira M ^a   Alameldeen, Alaa R ^a   Wilkerson, Chris ^a   Kulkarni, Jaydeep ^a   Jimenez, Daniel A ^b  

^a INTEL CORPORATION   (United States)

^b TEXAS A AND M UNIVERSITY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CACHE ARCHITECTURE; CACHE RELIABILITY; CACHE REPLACEMENT POLICY; CAPACITY REDUCTION; MULTI-CORE PROCESSOR; MULTI-CORE SYSTEMS; PERFORMANCE LOSS; POWER CONSTRAINTS;

CACHE MEMORY; CELLS; COMPUTER ARCHITECTURE; MICROPROCESSOR CHIPS; SUPERCOMPUTERS;

CYTOLOGY;

EID: 84880255927     PISSN: 15300897     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/HPCA.2013.6522312     Document Type: Conference Paper

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