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Volumn 15, Issue , 2010, Pages 90-100

WCET Analysis of a Parallel 3D Multigrid Solver Executed on the MERASA Multi-Core

Author keywords

[No Author keywords available]

Indexed keywords

COMMUNICATION AND SYNCHRONIZATIONS; MULTI-CORE PROCESSOR; MULTIGRID SOLVER; PARALLEL APPLICATION; PERFORMANCE REQUIREMENTS; PRELIMINARY ANALYSIS; SYSTEM SOFTWARES; WCET ANALYSIS;

EID: 84880109528     PISSN: 21906807     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.4230/OASIcs.WCET.2010.90     Document Type: Conference Paper
Times cited : (19)

References (13)
  • 3
    • 77649302111 scopus 로고    scopus 로고
    • Using bypass to tighten WCET estimates for multi-core processors with shared instruction caches
    • Hardy D., Piquet T., Puaut I.: Using Bypass to Tighten WCET Estimates for Multi-Core Processors with Shared Instruction Caches. In: IEEE Real-Time Systems Symposium (RTSS), 2009.
    • (2009) IEEE Real-Time Systems Symposium (RTSS)
    • Hardy, D.1    Piquet, T.2    Puaut, I.3
  • 9
    • 51549114926 scopus 로고    scopus 로고
    • Exploring locking and partitioning for predictable shared caches on multi-cores
    • Suhendra V., Mitra T.: Exploring Locking and Partitioning for Predictable Shared Caches on Multi-cores. In: 45th Conf. on Design Automation (DAC), 2008.
    • (2008) 45th Conf. on Design Automation (DAC)
    • Suhendra, V.1    Mitra, T.2


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.