Efficient moment estimation with extremely small sample size via bayesian inference for analog/mixed-signal validation

Proceedings - Design Automation Conference

Volumn , Issue , 2013, Pages

  Gu, Chenjie ^a   Chiprout, Eli ^a   Li, Xin ^b  

^a INTEL CORPORATION   (United States)

^b CARNEGIE MELLON UNIVERSITY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ANALOG/MIXED-SIGNAL CIRCUITS; BAYESIAN FRAMEWORKS; CIRCUIT CONFIGURATIONS; CIRCUIT PERFORMANCE; MAXIMUM A POSTERIORI ESTIMATION; POST-SILICON VALIDATIONS; PROBABILITY OF FAILURE; SIMULATIONS AND MEASUREMENTS;

BAYESIAN NETWORKS; COMPUTER AIDED DESIGN; INFERENCE ENGINES; SILICON;

ESTIMATION;

EID: 84879846624     PISSN: 0738100X     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/2463209.2488813     Document Type: Conference Paper

References (15)

1. A. Papoulis and S. Pillai, Probability, Random Variables and Stochastic Processes. McGraw-Hill Science/Engineering/Math, 2001.
2. G. Balamurugan, B. Casper, J. Jaussi, M. Mansuri, F. O'Mahony, and J. Kennedy, "Modeling and Analysis of High-Speed I/O Links, " Advanced Packaging, IEEE Transactions on, vol. 32, no. 2, pp. 237 -247, May 2009.
3. J. Keshava, N. Hakim, and C. Prudvi, "Post-Silicon Validation Challenges: How EDA and Academia can Help, " in Design Automation Conference (DAC), 2010 47th ACM/IEEE, June 2010, pp. 3 -7.
4. C. Gu, "Challenges in Post-Silicon Validation of High-Speed I/O Links, " in Computer-Aided Design (ICCAD), 2012 IEEE/ACM International Conference on. IEEE, 2012.
5. Intel Corp., "Intel Platform and Component Validation." [Online]. Available: http://download.intel.com/design/chipsets/labtour/ PVPTWhitePaper.pdf.
6. E. E. Lior Shkolnitsky, "Electrical System-Validation Methodology for Embedded DisplayPort, " June 2010.[Online]. Available: http://download.intel.com/design/intarch/PAPERS/323931.pdf.
7. K. Gambill, "System Margin Validation, " December 2008. [Online]. Available: http://download.intel.com/design/intarch/papers/321078.pdf.
8. W. Zhang, T. Chen, M. Ting, and X. Li, "Toward Efficient Large-Scale Performance Modeling of Integrated Circuits via Multi-Mode/Multi-Corner Sparse Regression, " in Design Automation Conference (DAC), 2010 47th ACM/IEEE. IEEE, 2010, pp. 897-902.
9. X. Li, W. Zhang, F. Wang, S. Sun, and C. Gu, "Efficient Parametric Yield Estimation of Analog/Mixed-Signal Circuits via Bayesian Model Fusion, " in Computer-Aided Design (ICCAD), 2012 IEEE/ACM International Conference on. IEEE, 2012.
10. [Online]. Available: http://www.pcisig.com.
11. [Online]. Available: http://www.jedec.org.
12. C. Bishop, Pattern Recognition and Machine Learning. Springer, New York, 2006, vol. 4.
13. G. Casella, "An Introduction to Empirical Bayes Data Analysis, " The American Statistician, vol. 39, no. 2, pp. 83-87, 1985.
14. B. Efron and C. Morris, "Data Analysis using Stein's Estimator and Its Generalizations, " Journal of the American Statistical Association, vol. 70, no. 350, pp. 311-319, 1975.
15. S. Arlot and A. Celisse, "A Survey of Cross-Validation Procedures for Model Selection, " Statistics Surveys, vol. 4, pp. 40-79, 2010.