Self-amplified dual gate charge trap flash memory for low-voltage operation

IEEE Electron Device Letters

Volumn 34, Issue 6, 2013, Pages 756-758

  Jang, Ki Hyun ^a   Jang, Hyun June ^a   Park, Jin Kwon ^a   Cho, Won Ju ^a  

^a Kwangwoon University   (South Korea)

Author keywords

Buried oxide (BOX); capacitive coupling; charge trap Flash (CTF); coupling ratio; dual gate (DG); silicon on insulator (SOI)

Indexed keywords

BURIED OXIDES; CAPACITIVE COUPLINGS; CHARGE TRAP FLASH (CTF); COUPLING RATIOS; DUAL-GATE (DG); SILICON-ON-INSULATORS;

FLASH MEMORY;

CHARGE TRAPPING;

EID: 84878303393     PISSN: 07413106     EISSN: None     Source Type: Journal    
DOI: 10.1109/LED.2013.2256770     Document Type: Article

References (8)

1. E. Suzuki, K. Ishii, S. Kanemaru, T. Maeda, T. Tsutsumi, T. Sekigawa, K. Nagai, and H. Hiroshima, "High suppressed short-channel effects in ultrathin SOI-n-MOSFET's," IEEE Trans. Electron Devices, vol. 47, no. 2, pp. 354-359, Feb. 2000. (Pubitemid 30556156)
2. M. J. Kumar and A. Chaudry, "Two-dimensional analytical modeling of fully depleted DMG SOI MOSFET and evidence for diminished SCEs," IEEE Trans. Electron Devices, vol. 51, no. 4, pp. 569-574, Apr. 2004.
3. H.-K. Lim and J. G. Fossum, "Threshold voltage of thin-film silicon-on-insulator (SOI) MOSFET's," IEEE Trans. Electron Devices, vol. 30, no. 10, pp. 1244-1251, Oct. 1983.
4. J. Jung and W.-J. Cho, "Tunnel barrier engineering for non-volatile memory," J. Semicond. Technol. Sci., vol. 8, no. 1, pp. 32-39, Mar. 2008.
5. J.-P. Colinge, "The SOI MOSFET," in Silicon-On-Insulator Technology: Material to VLSI, 3rd ed. London, U.K.: Kluwer, 2004, pp. 159-166.
6. M. Chang, T.-W. Kim, J. Lee, M. Jo, S. Kim, S. Jung, H. Choi, T. Lee, and H. Hwang, "Data retention characteristics of MANOS-type Flash memory device with different metal gates at various levels of charge injection," Microelectron. Eng., vol. 86, no. 7, pp. 1804-1806, Jul. 2009.
7. G.-H. Park and W.-J. Cho, "Reliability of modified tunneling barriers for high performance nonvolatile charge trap Flash memory application," Appl. Phys. Lett., vol. 96, no. 4, pp. 043503-1-043503-3, Jan. 2010.
8. Z. Lun, D. S. Ang, and C. H. Ling, "A novel subthreshold slope technique for the extraction of the buried-oxide interface trap density in the fully depleted SOI MOSFET," IEEE Electron Device Lett., vol. 21, no. 8, pp. 411-413, Aug. 2000.