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Volumn 56, Issue , 2013, Pages 354-355

A 57.9-to-68.3GHz 24.6mW frequency synthesizer with in-phase injection-coupled QVCO in 65nm CMOS

Author keywords

[No Author keywords available]

Indexed keywords

CONVENTIONAL TECHNIQUES; DIRECT-CONVERSION TRANSCEIVERS; FULLY INTEGRATED; MM-WAVE APPLICATION; MM-WAVE FREQUENCIES; PARALLEL-COUPLED; QUADRATURE SIGNAL; SIGNAL GENERATION;

EID: 84876542655     PISSN: 01936530     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ISSCC.2013.6487767     Document Type: Conference Paper
Times cited : (36)

References (7)
  • 1
    • 34548276409 scopus 로고    scopus 로고
    • The quadrature lc oscillator: A complete portrait based on injection locking
    • Sept
    • A. Mirzaei, et al., "The Quadrature LC Oscillator: A Complete Portrait Based on Injection Locking," IEEE J. Solid-State Circuits, vol. 42, no. 9, pp. 1916-1932, Sept. 2007
    • (2007) IEEE J. Solid-State Circuits , vol.42 , Issue.9 , pp. 1916-1932
    • Mirzaei, A.1
  • 2
    • 82155173488 scopus 로고    scopus 로고
    • A low-noise quadrature vco based on magnetically coupled resonators and a wideband frequency divider at millimeter waves
    • Dec
    • U. Decanis, et al., "A Low-Noise Quadrature VCO Based on Magnetically Coupled Resonators and a Wideband Frequency Divider at Millimeter Waves," IEEE J. Solid-State Circuits, vol. 46, no. 12, pp. 2943-2955, Dec. 2011
    • (2011) IEEE J. Solid-State Circuits , vol.46 , Issue.12 , pp. 2943-2955
    • Decanis, U.1
  • 3
    • 57849086993 scopus 로고    scopus 로고
    • Low-spur, low-phase-noise clock multiplier based on a combination of pll and recirculating dll with dual-pulse ring oscillator and self-correcting charge pump
    • Dec
    • S. L.J. Gierkink, "Low-Spur, Low-Phase-Noise Clock Multiplier Based on a Combination of PLL and Recirculating DLL with Dual-Pulse Ring Oscillator and Self-Correcting Charge Pump," IEEE J. Solid-State Circuits, vol. 43, no. 12, pp. 2967-2976, Dec. 2008
    • (2008) IEEE J. Solid-State Circuits , vol.43 , Issue.12 , pp. 2967-2976
    • Gierkink, S.L.J.1
  • 4
    • 70349297486 scopus 로고    scopus 로고
    • A 57-To-66ghz quadrature pll in 45nm digital cmos
    • Feb
    • K. Scheir, et al., "A 57-To-66GHz Quadrature PLL in 45nm Digital CMOS," ISSCC Dig. Tech. Papers, pp. 494-495, Feb. 2011
    • (2011) ISSCC Dig. Tech. Papers , pp. 494-495
    • Scheir, K.1
  • 5
    • 72949089983 scopus 로고    scopus 로고
    • A 90 nm cmos low-power 60ghz transceiver with integrated baseband circuitry
    • Dec
    • C. Marcu, et al., "A 90 nm CMOS Low-Power 60GHz Transceiver with Integrated Baseband Circuitry," IEEE J. Solid-State Circuits, vol. 44, no. 12, pp. 3434-3447. Dec. 2009
    • (2009) IEEE J. Solid-State Circuits , vol.44 , Issue.12 , pp. 3434-3447
    • Marcu, C.1
  • 6
    • 79955721012 scopus 로고    scopus 로고
    • A 60ghz 16qam/8psk/qpsk/bpsk direct-conversion transceiver for
    • Feb
    • K. Okada, et al., "A 60GHz 16QAM/8PSK/QPSK/BPSK Direct-Conversion Transceiver for IEEE 802.15.3c," ISSCC Dig. Tech. Papers, pp. 160-161, Feb. 2011
    • (2011) IEEE 802.15.3c ISSCC Dig. Tech. Papers , pp. 160-161
    • Okada, K.1
  • 7
    • 84860667304 scopus 로고    scopus 로고
    • A low-power 57-To-66ghz transceiver in 40nm lp cmos with-17db evm at 7gb/s
    • Feb
    • V. Vidojkovic, et al., "A Low-Power 57-To-66GHz Transceiver in 40nm LP CMOS with-17dB EVM at 7Gb/s," ISSCC Dig. Tech. Papers, pp. 268-269, Feb. 2012
    • (2012) ISSCC Dig. Tech. Papers , pp. 268-269
    • Vidojkovic, V.1


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.